diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 6e4c380d98..3809c61d63 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -34,6 +34,7 @@
 #include <set>
 #include <sstream>
 
+#include "arch/riscv/faults.hh"
 #include "arch/riscv/interrupts.hh"
 #include "arch/riscv/mmu.hh"
 #include "arch/riscv/pagetable.hh"
@@ -723,6 +724,12 @@ ISA::globalClearExclusive()
     tc->getCpuPtr()->wakeup(tc->threadId());
 }
 
+void
+ISA::resetThread()
+{
+    Reset().invoke(tc);
+}
+
 } // namespace RiscvISA
 } // namespace gem5
 
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index e332956972..5a2a610479 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -127,6 +127,8 @@ class ISA : public BaseISA
 
     void globalClearExclusive() override;
 
+    void resetThread() override;
+
     RiscvType rvType() const { return rv_type; }
 };