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Enhancements to python config proxy class.

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python/m5/config.py:
    - Enhanced Proxy class now supports subscripting, e.g.,
    parent.cpu[0] or even parent.cpu[0].icache.

    - Proxy also supports multiplication (e.g., parent.cycle * 3),
    though this feature has not been tested.

    - Subscript 0 works even on non-lists, so you can safely say
    cpu[0] and get the first cpu even if there's only one.

    - Changed name of proxy object from 'Super' to 'parent', and
    changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
    Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').

--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
This commit is contained in:
Steve Reinhardt
2005-03-16 00:40:48 -05:00
parent 42753edb3c
commit c8538d6a7e
15 changed files with 118 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
python/m5/objects/AlphaConsole.mpy
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@@ -2,8 +2,8 @@ from Device import PioDevice
simobj AlphaConsole(PioDevice):
type = 'AlphaConsole'
cpu = Param.BaseCPU(Super, "Processor")
cpu = Param.BaseCPU(parent.any, "Processor")
disk = Param.SimpleDisk("Simple Disk")
num_cpus = Param.Int(1, "Number of CPUs")
sim_console = Param.SimConsole(Super, "The Simulator Console")
system = Param.BaseSystem(Super, "system object")
sim_console = Param.SimConsole(parent.any, "The Simulator Console")
system = Param.BaseSystem(parent.any, "system object")

2
python/m5/objects/BaseCPU.mpy
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@@ -8,7 +8,7 @@ simobj BaseCPU(SimObject):
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
mem = Param.FunctionalMemory("memory")
system = Param.BaseSystem(Super, "system object")
system = Param.BaseSystem(parent.any, "system object")
else:
workload = VectorParam.Process("processes to run")

4
python/m5/objects/BaseSystem.mpy
View File

@@ -1,8 +1,8 @@
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
memctrl = Param.MemoryController(Super, "memory controller")
physmem = Param.PhysicalMemory(Super, "phsyical memory")
memctrl = Param.MemoryController(parent.any, "memory controller")
physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
kernel = Param.String("file that contains the kernel code")
console = Param.String("file that contains the console code")
pal = Param.String("file that contains palcode")

4
python/m5/objects/Device.mpy
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@@ -14,7 +14,7 @@ simobj FooPioDevice(FunctionalMemory):
type = 'PioDevice'
abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Super, "Memory Controller")
mmu = Param.MemoryController(parent.any, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
@@ -25,7 +25,7 @@ simobj FooDmaDevice(FooPioDevice):
simobj PioDevice(FooPioDevice):
type = 'PioDevice'
abstract = True
platform = Param.Platform(Super, "Platform")
platform = Param.Platform(parent.any, "Platform")
simobj DmaDevice(PioDevice):
type = 'DmaDevice'

6
python/m5/objects/Ethernet.mpy
View File

@@ -49,8 +49,8 @@ simobj EtherDev(DmaDevice):
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
tlaser = Param.Turbolaser(Super, "Turbolaser")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
tlaser = Param.Turbolaser(parent.any, "Turbolaser")
simobj NSGigE(PciDevice):
type = 'NSGigE'
@@ -73,7 +73,7 @@ simobj NSGigE(PciDevice):
intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
simobj EtherDevInt(EtherInt):
type = 'EtherDevInt'

2
python/m5/objects/Ide.mpy
View File

@@ -7,7 +7,7 @@ simobj IdeDisk(SimObject):
delay = Param.Tick(1, "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(Super, "Physical memory")
physmem = Param.PhysicalMemory(parent.any, "Physical memory")
simobj IdeController(PciDevice):
type = 'IdeController'

2
python/m5/objects/IntrControl.mpy
View File

@@ -1,3 +1,3 @@
simobj IntrControl(SimObject):
type = 'IntrControl'
cpu = Param.BaseCPU(Super, "the cpu")
cpu = Param.BaseCPU(parent.any, "the cpu")

4
python/m5/objects/Pci.mpy
View File

@@ -47,5 +47,5 @@ simobj PciDevice(DmaDevice):
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
configdata = Param.PciConfigData(Super, "PCI Config data")
configspace = Param.PciConfigAll(Super, "PCI Configspace")
configdata = Param.PciConfigData(parent.any, "PCI Config data")
configspace = Param.PciConfigAll(parent.any, "PCI Configspace")

2
python/m5/objects/PhysicalMemory.mpy
View File

@@ -4,4 +4,4 @@ simobj PhysicalMemory(FunctionalMemory):
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
mmu = Param.MemoryController(Super, "Memory Controller")
mmu = Param.MemoryController(parent.any, "Memory Controller")

2
python/m5/objects/Platform.mpy
View File

@@ -2,4 +2,4 @@ simobj Platform(SimObject):
type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(Super, "interrupt controller")
intrctrl = Param.IntrControl(parent.any, "interrupt controller")

2
python/m5/objects/SimConsole.mpy
View File

@@ -5,7 +5,7 @@ simobj ConsoleListener(SimObject):
simobj SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Super, "interrupt controller")
intr_control = Param.IntrControl(parent.any, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
output = Param.String('console', "file to dump output to")

2
python/m5/objects/SimpleDisk.mpy
View File

@@ -1,4 +1,4 @@
simobj SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")

8
python/m5/objects/Tsunami.mpy
View File

@@ -4,12 +4,12 @@ from Platform import Platform
simobj Tsunami(Platform):
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(Super, "system")
system = Param.BaseSystem(parent.any, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
tsunami = Param.Tsunami(Super, "Tsunami")
tsunami = Param.Tsunami(parent.any, "Tsunami")
simobj TsunamiFake(FooPioDevice):
type = 'TsunamiFake'
@@ -18,8 +18,8 @@ simobj TsunamiIO(FooPioDevice):
type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Super, "Tsunami")
tsunami = Param.Tsunami(parent.any, "Tsunami")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Super, "Tsunami")
tsunami = Param.Tsunami(parent.any, "Tsunami")

2
python/m5/objects/Uart.mpy
View File

@@ -2,5 +2,5 @@ from Device import PioDevice
simobj Uart(PioDevice):
type = 'Uart'
console = Param.SimConsole(Super, "The console")
console = Param.SimConsole(parent.any, "The console")
size = Param.Addr(0x8, "Device size")