From c853187273bb88118704b1af53cfc3b6e1ea0d29 Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Thu, 2 Feb 2023 04:50:19 -0800
Subject: [PATCH] arch: Add a virtual method to the BaseISA to reset its
 ThreadContext.

This will be used as part of a generic CPU reset mechanism.

Change-Id: I010f6bdaca0cbb6be1799ccdc345c4828515209d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67572
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/generic/isa.hh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index e4e7929385..e9e4d95d7b 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -43,6 +43,7 @@
 #include <vector>
 
 #include "arch/generic/pcstate.hh"
+#include "base/logging.hh"
 #include "cpu/reg_class.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -83,6 +84,8 @@ class BaseISA : public SimObject
     virtual bool inUserMode() const = 0;
     virtual void copyRegsFrom(ThreadContext *src) = 0;
 
+    virtual void resetThread() { panic("Thread reset not implemented."); }
+
     const RegClasses &regClasses() const { return _regClasses; }
 
     // Locked memory handling functions.