mem: Delay deleting of incoming packets by one call.
This patch is a temporary fix until Andreas' four-phase patches get reviewed and committed. Removing FastAlloc seems to have exposed an issue which previously was reasonable rare in which packets are freed before the sending cache is done with them. This change puts incoming packets no a pendingDelete queue which are deleted at the start of the next call and thus breaks the dependency between when the caller returns true and when the packet is actually used by the sending cache. Running valgrind on a multi-core linux boot and the memtester results in no valgrind warnings.
This commit is contained in:
7
src/mem/cache/cache.hh
vendored
7
src/mem/cache/cache.hh
vendored
@@ -190,6 +190,13 @@ class Cache : public BaseCache
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*/
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const bool prefetchOnAccess;
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/**
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* @todo this is a temporary workaround until the 4-phase code is committed.
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* upstream caches need this packet until true is returned, so hold it for
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* deletion until a subsequent call
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*/
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std::vector<PacketPtr> pendingDelete;
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/**
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* Does all the processing necessary to perform the provided request.
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* @param pkt The memory request to perform.
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18
src/mem/cache/cache_impl.hh
vendored
18
src/mem/cache/cache_impl.hh
vendored
@@ -378,6 +378,13 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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//@todo Add back in MemDebug Calls
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// MemDebug::cacheAccess(pkt);
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/// @todo temporary hack to deal with memory corruption issue until
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/// 4-phase transactions are complete
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for (int x = 0; x < pendingDelete.size(); x++)
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delete pendingDelete[x];
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pendingDelete.clear();
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// we charge hitLatency for doing just about anything here
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Tick time = curTick() + hitLatency;
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@@ -421,7 +428,11 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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}
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// since we're the official target but we aren't responding,
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// delete the packet now.
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delete pkt;
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/// @todo nominally we should just delete the packet here,
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/// however, until 4-phase stuff we can't because sending
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/// cache is still relying on it
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pendingDelete.push_back(pkt);
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return true;
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}
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@@ -489,7 +500,10 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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pkt->makeTimingResponse();
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cpuSidePort->respond(pkt, curTick()+lat);
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} else {
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delete pkt;
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/// @todo nominally we should just delete the packet here,
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/// however, until 4-phase stuff we can't because sending
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/// cache is still relying on it
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pendingDelete.push_back(pkt);
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}
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} else {
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// miss
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@@ -62,6 +62,12 @@ SimpleTimingPort::recvFunctional(PacketPtr pkt)
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bool
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SimpleTimingPort::recvTimingReq(PacketPtr pkt)
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{
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/// @todo temporary hack to deal with memory corruption issue until
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/// 4-phase transactions are complete. Remove me later
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for (int x = 0; x < pendingDelete.size(); x++)
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delete pendingDelete[x];
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pendingDelete.clear();
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if (pkt->memInhibitAsserted()) {
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// snooper will supply based on copy of packet
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// still target's responsibility to delete packet
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@@ -78,7 +84,10 @@ SimpleTimingPort::recvTimingReq(PacketPtr pkt)
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assert(pkt->isResponse());
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queue.schedSendTiming(pkt, curTick() + latency);
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} else {
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delete pkt;
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/// @todo nominally we should just delete the packet here.
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/// Until 4-phase stuff we can't because the sending
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/// cache is still relying on it
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pendingDelete.push_back(pkt);
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}
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return true;
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@@ -73,6 +73,14 @@ class SimpleTimingPort : public QueuedSlavePort
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virtual Tick recvAtomic(PacketPtr pkt) = 0;
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/**
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* @todo this is a temporary workaround until the 4-phase code is committed.
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* upstream caches need this packet until true is returned, so hold it for
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* deletion until a subsequent call
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*/
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std::vector<PacketPtr> pendingDelete;
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public:
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/**
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