arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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@@ -1,4 +1,4 @@
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# Copyright (c) 2010 ARM Limited
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# Copyright (c) 2010, 2017 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@@ -86,6 +86,7 @@ class SIMD_Unit(FUDesc):
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OpDesc(opClass='SimdMultAcc'),
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OpDesc(opClass='SimdShift'),
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OpDesc(opClass='SimdShiftAcc'),
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OpDesc(opClass='SimdDiv'),
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OpDesc(opClass='SimdSqrt'),
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OpDesc(opClass='SimdFloatAdd'),
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OpDesc(opClass='SimdFloatAlu'),
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@@ -95,9 +96,18 @@ class SIMD_Unit(FUDesc):
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OpDesc(opClass='SimdFloatMisc'),
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OpDesc(opClass='SimdFloatMult'),
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OpDesc(opClass='SimdFloatMultAcc'),
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OpDesc(opClass='SimdFloatSqrt') ]
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OpDesc(opClass='SimdFloatSqrt'),
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OpDesc(opClass='SimdReduceAdd'),
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OpDesc(opClass='SimdReduceAlu'),
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OpDesc(opClass='SimdReduceCmp'),
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OpDesc(opClass='SimdFloatReduceAdd'),
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OpDesc(opClass='SimdFloatReduceCmp') ]
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count = 4
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class PredALU(FUDesc):
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opList = [ OpDesc(opClass='SimdPredAlu') ]
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count = 1
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class ReadPort(FUDesc):
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opList = [ OpDesc(opClass='MemRead'),
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OpDesc(opClass='FloatMemRead') ]
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