arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/decoder.hh

@@ -72,6 +72,12 @@ class Decoder
     int fpscrLen;
     int fpscrStride;
 
+    /**
+     * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
+     * bitfields.
+     */
+    int sveLen;
+
     Enums::DecoderFlavour decoderFlavour;
 
     /// A cache of decoded instruction objects.
@@ -197,6 +203,11 @@ class Decoder
         fpscrLen = fpscr.len;
         fpscrStride = fpscr.stride;
     }
+
+    void setSveLen(uint8_t len)
+    {
+        sveLen = len;
+    }
 };
 
 } // namespace ArmISA