arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/decoder.cc

@@ -47,6 +47,7 @@
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "debug/Decoder.hh"
+#include "sim/full_system.hh"
 
 namespace ArmISA
 {
@@ -54,11 +55,13 @@ namespace ArmISA
 GenericISA::BasicDecodeCache Decoder::defaultCache;
 
 Decoder::Decoder(ISA* isa)
-    : data(0), fpscrLen(0), fpscrStride(0), decoderFlavour(isa
-            ? isa->decoderFlavour()
-            : Enums::Generic)
+    : data(0), fpscrLen(0), fpscrStride(0),
+      decoderFlavour(isa->decoderFlavour())
 {
     reset();
+
+    // Initialize SVE vector length
+    sveLen = (isa->getCurSveVecLenInBitsAtReset() >> 7) - 1;
 }
 
 void
@@ -157,6 +160,7 @@ Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     emi.aarch64 = pc.aarch64();
     emi.fpscrLen = fpscrLen;
     emi.fpscrStride = fpscrStride;
+    emi.sveLen = sveLen;
 
     const Addr alignment(pc.thumb() ? 0x1 : 0x3);
     emi.decoderFault = static_cast<uint8_t>(