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Implement a state machine clock that acutally limits how fast

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the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.

dev/ns_gige.cc:
    Implement a state machine clock that acutally limits how fast
    the state machine can run.  After each state transition, a
    variable is kept to hold the next state transition until the
    next clock.  The frequency is of the actual state transitions,
    and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
    Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
    Default the state machine clock to '0ns' so the default
    behaviour doesn't change when we actually implement the
    state machine clock.

--HG--
extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd
This commit is contained in:
Nathan Binkert
2005-06-27 17:02:40 -04:00
parent 5ea3c1c8f3
commit c4029ecb30
3 changed files with 52 additions and 22 deletions
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2
python/m5/objects/Ethernet.py
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@@ -64,7 +64,7 @@ class NSGigE(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
clock = Param.Clock('100MHz', "State machine processor frequency")
clock = Param.Clock('0ns', "State machine processor frequency")
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")