From c3eee3ca5a54d38fccae020441ed5b4625416eaf Mon Sep 17 00:00:00 2001
From: Tom Rollet <tom.rollet@huawei.com>
Date: Tue, 1 Jun 2021 15:04:51 +0200
Subject: [PATCH] cpu-o3: fix commit DPRINTF ROB arguments order

Change-Id: I7a2bacc5d7e3d8bab47adb762d3f88f2b2fd6e1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46599
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/cpu/o3/commit.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index 4647adb1c1..ce624dacd9 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -1342,7 +1342,7 @@ Commit::getInsts()
             changedROBNumEntries[tid] = true;
 
             DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
-                    inst->seqNum, tid, inst->pcState());
+                    tid, inst->seqNum, inst->pcState());
 
             rob->insertInst(inst);
 
@@ -1352,7 +1352,7 @@ Commit::getInsts()
         } else {
             DPRINTF(Commit, "[tid:%i] [sn:%llu] "
                     "Instruction PC %s was squashed, skipping.\n",
-                    inst->seqNum, tid, inst->pcState());
+                    tid, inst->seqNum, inst->pcState());
         }
     }
 }