Merge with the main repo.
--HG-- rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
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@@ -41,14 +41,14 @@ Source('mport.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('tport.cc')
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Source('vport.cc')
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Source('fs_translating_port_proxy.cc')
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Source('se_translating_port_proxy.cc')
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if env['TARGET_ISA'] != 'no':
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SimObject('PhysicalMemory.py')
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Source('dram.cc')
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Source('page_table.cc')
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Source('physical.cc')
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Source('translating_port.cc')
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DebugFlag('Bus')
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DebugFlag('BusAddrRanges')
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