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Merge with the main repo.

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--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
This commit is contained in:
Gabe Black
2012-01-28 07:24:01 -08:00
parent da2a4acc26 4acca8a053
commit c3d41a2def
717 changed files with 16788 additions and 13793 deletions
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7
src/cpu/BaseCPU.py
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@@ -138,9 +138,12 @@ class BaseCPU(MemObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
_cached_ports = []
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports = ["itb.walker.port", "dtb.walker.port"]
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_ports = []
if buildEnv['TARGET_ISA'] == 'x86':