diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e52cd49456..2b3dcc6a16 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -302,20 +302,25 @@ class BaseCPU(ClockedObject):
 
         # Practically speaking, these ports will exist on the x86 interrupt
         # controller class.
+        # Note: _uncached_interrupt_response_ports is a *class* variable
+        # not a *instance* variable. Thus, we cannot use `extend` here.
         if "pio" in self.ArchInterrupts._ports:
-            self._uncached_interrupt_response_ports.extend(
-                [f"interrupts[{i}].pio" for i in range(self.numThreads)]
+            self._uncached_interrupt_response_ports = (
+                self._uncached_interrupt_response_ports
+                + [f"interrupts[{i}].pio" for i in range(self.numThreads)]
             )
         if "int_responder" in self.ArchInterrupts._ports:
-            self._uncached_interrupt_response_ports.extend(
-                [
+            self._uncached_interrupt_response_ports = (
+                self._uncached_interrupt_response_ports
+                + [
                     f"interrupts[{i}].int_responder"
                     for i in range(self.numThreads)
                 ]
             )
         if "int_requestor" in self.ArchInterrupts._ports:
-            self._uncached_interrupt_request_ports.extend(
-                [
+            self._uncached_interrupt_request_ports = (
+                self._uncached_interrupt_request_ports
+                + [
                     f"interrupts[{i}].int_requestor"
                     for i in range(self.numThreads)
                 ]