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tests, configs, util, mem, python, systemc: Change base 10 units to base 2 (#1605)

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This commit changes metric units (e.g. kB, MB, and GB) to binary units
(KiB, MiB, GiB) in various files. This PR covers files that were missed
by a previous PR that also made these changes.
This commit is contained in:
Erin (Jianghua) Le
2024-10-01 11:18:05 -07:00
committed by GitHub
parent d57208c615
commit c10feed524
45 changed files with 135 additions and 129 deletions
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10
tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py
View File

@@ -135,7 +135,7 @@ elif args.mem_system == "chi":
)
cache_hierarchy = PrivateL1CacheHierarchy(
size="16kB",
size="16KiB",
assoc=4,
)
@@ -146,11 +146,11 @@ elif args.mem_system == "mesi_two_level":
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="32kB",
l1d_size="32KiB",
l1d_assoc=8,
l1i_size="32kB",
l1i_size="32KiB",
l1i_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=2,
)
@@ -161,7 +161,7 @@ elif args.mem_system == "mi_example":
MIExampleCacheHierarchy,
)
cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=4)
cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=4)
else:
raise NotImplementedError(
f"Memory type '{args.mem_system}' is not supported in the boot tests."

4
tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py
View File

@@ -55,11 +55,11 @@ requires(isa_required=ISA.X86)
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="1GB")
memory = SingleChannelDDR3_1600(size="1GiB")
# Setup a single core Processor.
processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)

4
tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py
View File

@@ -64,11 +64,11 @@ requires(isa_required=ISA.X86)
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="1GB")
memory = SingleChannelDDR3_1600(size="1GiB")
# Setup a single core Processor.
processor = SimpleProcessor(cpu_type=CPUTypes.O3, isa=ISA.X86, num_cores=1)

8
tests/gem5/cpu_tests/run.py
View File

@@ -55,7 +55,7 @@ class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the default size
size = "32kB"
size = "32KiB"
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU icache port"""
@@ -66,7 +66,7 @@ class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the default size
size = "32kB"
size = "32KiB"
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU dcache port"""
@@ -77,7 +77,7 @@ class L2Cache(Cache):
"""Simple L2 Cache with default values"""
# Default parameters
size = "512kB"
size = "512KiB"
assoc = 16
tag_latency = 10
data_latency = 10
@@ -134,7 +134,7 @@ if args.cpu not in (
):
system.mem_mode = "timing"
system.mem_ranges = [AddrRange("512MB")]
system.mem_ranges = [AddrRange("512MiB")]
system.cpu = valid_cpu[args.cpu]()

2
tests/gem5/fs/linux/arm/configs/base_caches.py
View File

@@ -81,5 +81,5 @@ class IOCache(Cache):
data_latency = 50
response_latency = 50
mshrs = 20
size = "1kB"
size = "1KiB"
tgts_per_mshr = 12

22
tests/gem5/fs/linux/arm/configs/base_config.py
View File

@@ -114,7 +114,7 @@ class BaseSystem(metaclass=ABCMeta):
cpu -- CPU instance to work on.
"""
cpu.addPrivateSplitL1Caches(
L1_ICache(size="32kB", assoc=1), L1_DCache(size="32kB", assoc=4)
L1_ICache(size="32KiB", assoc=1), L1_DCache(size="32KiB", assoc=4)
)
def create_caches_shared(self, system):
@@ -128,7 +128,7 @@ class BaseSystem(metaclass=ABCMeta):
"""
system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2c = L2Cache(
clk_domain=system.cpu_clk_domain, size="4MB", assoc=8
clk_domain=system.cpu_clk_domain, size="4MiB", assoc=8
)
system.l2c.cpu_side = system.toL2Bus.mem_side_ports
system.l2c.mem_side = system.membus.cpu_side_ports
@@ -197,9 +197,9 @@ class BaseSystem(metaclass=ABCMeta):
# Set the default cache size and associativity to be very
# small to encourage races between requests and writebacks.
args.l1d_size = "32kB"
args.l1i_size = "32kB"
args.l2_size = "4MB"
args.l1d_size = "3KiB"
args.l1i_size = "32KiB"
args.l2_size = "4MiB"
args.l1d_assoc = 4
args.l1i_assoc = 2
args.l2_assoc = 8
@@ -305,9 +305,9 @@ class BaseSESystemUniprocessor(BaseSESystem):
if self.mem_mode == "timing":
# @todo We might want to revisit these rather enthusiastic L1 sizes
cpu.addTwoLevelCacheHierarchy(
L1_ICache(size="128kB"),
L1_DCache(size="256kB"),
L2Cache(size="2MB"),
L1_ICache(size="128KiB"),
L1_DCache(size="256KiB"),
L2Cache(size="2MiB"),
)
def create_caches_shared(self, system):
@@ -367,9 +367,9 @@ class BaseFSSystemUniprocessor(BaseFSSystem):
def create_caches_private(self, cpu):
cpu.addTwoLevelCacheHierarchy(
L1_ICache(size="32kB", assoc=1),
L1_DCache(size="32kB", assoc=4),
L2Cache(size="4MB", assoc=8),
L1_ICache(size="32KiB", assoc=1),
L1_DCache(size="32KiB", assoc=4),
L2Cache(size="4MiB", assoc=8),
)
def create_caches_shared(self, system):

2
tests/gem5/gpu/test_gpu_apu_se.py
View File

@@ -108,7 +108,7 @@ gem5_verify_config(
resource_path,
"--reg-alloc-policy=dynamic",
"-n3",
"--mem-size=8GB",
"--mem-size=8GiB",
"--dgpu",
"--gfx-version",
"gfx900",

14
tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py
View File

@@ -128,18 +128,18 @@ if args.mem_system == "mi_example":
MIExampleCacheHierarchy,
)
cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
elif args.mem_system == "mesi_two_level":
from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
MESITwoLevelCacheHierarchy,
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="16kB",
l1d_size="16KiB",
l1d_assoc=8,
l1i_size="16kB",
l1i_size="16KiB",
l1i_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=1,
)
@@ -148,7 +148,9 @@ elif args.mem_system == "classic":
PrivateL1CacheHierarchy,
)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(
l1d_size="16KiB", l1i_size="16KiB"
)
else:
raise NotImplementedError(
f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -158,7 +160,7 @@ assert cache_hierarchy != None
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="3GB")
memory = SingleChannelDDR3_1600(size="3GiB")
processor = SimpleSwitchableProcessor(
starting_core_type=CPUTypes.KVM,

14
tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py
View File

@@ -114,18 +114,18 @@ if args.mem_system == "mi_example":
MIExampleCacheHierarchy,
)
cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
elif args.mem_system == "mesi_two_level":
from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
MESITwoLevelCacheHierarchy,
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="16kB",
l1d_size="16KiB",
l1d_assoc=8,
l1i_size="16kB",
l1i_size="16KiB",
l1i_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=1,
)
@@ -134,7 +134,9 @@ elif args.mem_system == "classic":
PrivateL1CacheHierarchy,
)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(
l1d_size="16KiB", l1i_size="16KiB"
)
else:
raise NotImplementedError(
f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -143,7 +145,7 @@ else:
assert cache_hierarchy != None
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="3GB")
memory = SingleChannelDDR3_1600(size="3GiB")
# Setup a Processor.
processor = SimpleSwitchableProcessor(

2
tests/gem5/m5threads_test_atomic/atomic_system.py
View File

@@ -48,7 +48,7 @@ root.system.clk_domain = SrcClockDomain()
root.system.clk_domain.clock = "3GHz"
root.system.clk_domain.voltage_domain = VoltageDomain()
root.system.mem_mode = "timing"
root.system.mem_ranges = [AddrRange("512MB")]
root.system.mem_ranges = [AddrRange("512MiB")]
if args.cpu_type == "DerivO3CPU":
root.system.cpu = [

4
tests/gem5/memory/memtest-run.py
View File

@@ -49,7 +49,7 @@ system.cpu_clk_domain = SrcClockDomain(
)
system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64kB", assoc=8)
system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64KiB", assoc=8)
system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
@@ -59,7 +59,7 @@ system.l2c.mem_side = system.membus.cpu_side_ports
for cpu in cpus:
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
cpu.l1c = L1Cache(size="32kB", assoc=4)
cpu.l1c = L1Cache(size="32KiB", assoc=4)
cpu.l1c.cpu_side = cpu.port
cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports

4
tests/gem5/memory/test.py
View File

@@ -41,10 +41,10 @@ gem5_verify_config(
)
simple_mem_params = [
("inf-bandwidth", {"bandwidth": "0GB/s"}),
("inf-bandwidth", {"bandwidth": "0GiB/s"}),
("low-latency", {"latency": "1ns"}),
("high-latency", {"latency": "1us"}),
("low-bandwidth", {"bandwidth": "1MB/s"}),
("low-bandwidth", {"bandwidth": "1MiB/s"}),
("high-var", {"latency_var": "100ns"}),
]

10
tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py
View File

@@ -151,7 +151,7 @@ if args.mem_system == "classic":
)
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="256kB"
l1d_size="32KiB", l1i_size="32KiB", l2_size="256KiB"
)
elif args.mem_system == "mesi_two_level":
from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
@@ -159,17 +159,17 @@ elif args.mem_system == "mesi_two_level":
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1i_size="32kB",
l1i_size="32KiB",
l1i_assoc=8,
l1d_size="32kB",
l1d_size="32KiB",
l1d_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=1,
)
# Setup the memory system.
memory = SingleChannelDDR3_1600(size="3GB")
memory = SingleChannelDDR3_1600(size="3GiB")
roi_type = get_cpu_type_from_str(args.cpu)
if args.boot_cpu != None:

6
tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py
View File

@@ -119,11 +119,11 @@ elif args.mem_system == "mesi_two_level":
# Setup the cache hierarchy.
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="16kB",
l1d_size="16KiB",
l1d_assoc=8,
l1i_size="16kB",
l1i_size="16KiB",
l1i_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=1,
)

2
tests/gem5/suite_tests/configs/suite_run_workload.py
View File

@@ -97,7 +97,7 @@ cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
)
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="3GB")
memory = SingleChannelDDR3_1600(size="3GiB")
def get_processor(isa):

4
tests/gem5/traffic_gen/configs/simple_traffic_run.py
View File

@@ -53,7 +53,7 @@ def generator_factory(
return LinearGenerator(
duration="250us",
rate="40GB/s",
rate="40GiB/s",
num_cores=generator_cores,
max_addr=mem_size,
)
@@ -62,7 +62,7 @@ def generator_factory(
return RandomGenerator(
duration="250us",
rate="40GB/s",
rate="40GiB/s",
num_cores=generator_cores,
max_addr=mem_size,
)

14
tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py
View File

@@ -128,18 +128,18 @@ if args.mem_system == "mi_example":
MIExampleCacheHierarchy,
)
cache_hierarchy = MIExampleCacheHierarchy(size="32kB", assoc=8)
cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
elif args.mem_system == "mesi_two_level":
from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
MESITwoLevelCacheHierarchy,
)
cache_hierarchy = MESITwoLevelCacheHierarchy(
l1d_size="16kB",
l1d_size="16KiB",
l1d_assoc=8,
l1i_size="16kB",
l1i_size="16KiB",
l1i_assoc=8,
l2_size="256kB",
l2_size="256KiB",
l2_assoc=16,
num_l2_banks=1,
)
@@ -148,7 +148,9 @@ elif args.mem_system == "classic":
PrivateL1CacheHierarchy,
)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(
l1d_size="16KiB", l1i_size="16KiB"
)
else:
raise NotImplementedError(
f"Memory system '{args.mem_system}' is not supported in the boot tests."
@@ -157,7 +159,7 @@ else:
assert cache_hierarchy != None
# Setup the system memory.
# Warning: This must be kept at 3GB for now. X86Motherboard does not support
# Warning: This must be kept at 3GiB for now. X86Motherboard does not support
# anything else right now!
python_module = "gem5.components.memory"
memory_class = getattr(importlib.import_module(python_module), args.dram_class)