From c028af111ad3de67fed8b2c525bbd2cba94cfcbc Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Wed, 8 Dec 2021 12:23:23 -0600 Subject: [PATCH] arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu This TLB is more of an "APU" TLB than anything GCN3 specific. It can be used with either GCN3 or Vega. With this change, VEGA_X86 builds and one can run binaries with Vega ISA code using the same steps as GCN3 but building the Vega ISA instead. Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53803 Maintainer: Bobby Bruce Reviewed-by: Matt Sinclair Maintainer: Matt Sinclair Tested-by: kokoro --- src/arch/amdgpu/common/SConscript | 43 +++++++++++++++++++ src/arch/amdgpu/{gcn3 => common}/X86GPUTLB.py | 4 +- src/arch/amdgpu/{gcn3 => common}/tlb.cc | 2 +- src/arch/amdgpu/{gcn3 => common}/tlb.hh | 0 .../amdgpu/{gcn3 => common}/tlb_coalescer.cc | 2 +- .../amdgpu/{gcn3 => common}/tlb_coalescer.hh | 2 +- src/arch/amdgpu/gcn3/SConscript | 4 -- src/arch/amdgpu/gcn3/gpu_isa.hh | 2 +- src/gpu-compute/compute_unit.cc | 1 + src/gpu-compute/fetch_unit.cc | 1 + src/gpu-compute/shader.cc | 1 + 11 files changed, 52 insertions(+), 10 deletions(-) create mode 100644 src/arch/amdgpu/common/SConscript rename src/arch/amdgpu/{gcn3 => common}/X86GPUTLB.py (97%) rename src/arch/amdgpu/{gcn3 => common}/tlb.cc (99%) rename src/arch/amdgpu/{gcn3 => common}/tlb.hh (100%) rename src/arch/amdgpu/{gcn3 => common}/tlb_coalescer.cc (99%) rename src/arch/amdgpu/{gcn3 => common}/tlb_coalescer.hh (99%) diff --git a/src/arch/amdgpu/common/SConscript b/src/arch/amdgpu/common/SConscript new file mode 100644 index 0000000000..f6f9cb68c7 --- /dev/null +++ b/src/arch/amdgpu/common/SConscript @@ -0,0 +1,43 @@ +# Copyright (c) 2021 Advanced Micro Devices, Inc. +# All rights reserved. +# +# For use for simulation and test purposes only +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from this +# software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +import sys + +Import('*') + +if not env['BUILD_GPU']: + Return() + +if env['TARGET_GPU_ISA'] == 'gcn3' or env['TARGET_GPU_ISA'] == 'vega': + SimObject('X86GPUTLB.py', sim_objects=['X86GPUTLB', 'TLBCoalescer']) + + Source('tlb.cc') + Source('tlb_coalescer.cc') diff --git a/src/arch/amdgpu/gcn3/X86GPUTLB.py b/src/arch/amdgpu/common/X86GPUTLB.py similarity index 97% rename from src/arch/amdgpu/gcn3/X86GPUTLB.py rename to src/arch/amdgpu/common/X86GPUTLB.py index 1c7f1d0247..b5f3387402 100644 --- a/src/arch/amdgpu/gcn3/X86GPUTLB.py +++ b/src/arch/amdgpu/common/X86GPUTLB.py @@ -39,7 +39,7 @@ from m5.SimObject import SimObject class X86GPUTLB(ClockedObject): type = 'X86GPUTLB' cxx_class = 'gem5::X86ISA::GpuTLB' - cxx_header = 'arch/amdgpu/gcn3/tlb.hh' + cxx_header = 'arch/amdgpu/common/tlb.hh' size = Param.Int(64, "TLB size (number of entries)") assoc = Param.Int(64, "TLB associativity") @@ -63,7 +63,7 @@ class X86GPUTLB(ClockedObject): class TLBCoalescer(ClockedObject): type = 'TLBCoalescer' cxx_class = 'gem5::TLBCoalescer' - cxx_header = 'arch/amdgpu/gcn3/tlb_coalescer.hh' + cxx_header = 'arch/amdgpu/common/tlb_coalescer.hh' probesPerCycle = Param.Int(2, "Number of TLB probes per cycle") coalescingWindow = Param.Int(1, "Permit coalescing across that many ticks") diff --git a/src/arch/amdgpu/gcn3/tlb.cc b/src/arch/amdgpu/common/tlb.cc similarity index 99% rename from src/arch/amdgpu/gcn3/tlb.cc rename to src/arch/amdgpu/common/tlb.cc index a6280da04e..e108a0b563 100644 --- a/src/arch/amdgpu/gcn3/tlb.cc +++ b/src/arch/amdgpu/common/tlb.cc @@ -32,7 +32,7 @@ * */ -#include "arch/amdgpu/gcn3/tlb.hh" +#include "arch/amdgpu/common/tlb.hh" #include #include diff --git a/src/arch/amdgpu/gcn3/tlb.hh b/src/arch/amdgpu/common/tlb.hh similarity index 100% rename from src/arch/amdgpu/gcn3/tlb.hh rename to src/arch/amdgpu/common/tlb.hh diff --git a/src/arch/amdgpu/gcn3/tlb_coalescer.cc b/src/arch/amdgpu/common/tlb_coalescer.cc similarity index 99% rename from src/arch/amdgpu/gcn3/tlb_coalescer.cc rename to src/arch/amdgpu/common/tlb_coalescer.cc index 9b53db8688..507d0e2b6f 100644 --- a/src/arch/amdgpu/gcn3/tlb_coalescer.cc +++ b/src/arch/amdgpu/common/tlb_coalescer.cc @@ -31,7 +31,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/amdgpu/gcn3/tlb_coalescer.hh" +#include "arch/amdgpu/common/tlb_coalescer.hh" #include diff --git a/src/arch/amdgpu/gcn3/tlb_coalescer.hh b/src/arch/amdgpu/common/tlb_coalescer.hh similarity index 99% rename from src/arch/amdgpu/gcn3/tlb_coalescer.hh rename to src/arch/amdgpu/common/tlb_coalescer.hh index afe12c942a..22f311c682 100644 --- a/src/arch/amdgpu/gcn3/tlb_coalescer.hh +++ b/src/arch/amdgpu/common/tlb_coalescer.hh @@ -39,7 +39,7 @@ #include #include -#include "arch/amdgpu/gcn3/tlb.hh" +#include "arch/amdgpu/common/tlb.hh" #include "arch/generic/tlb.hh" #include "arch/x86/isa.hh" #include "arch/x86/pagetable.hh" diff --git a/src/arch/amdgpu/gcn3/SConscript b/src/arch/amdgpu/gcn3/SConscript index e8e00020e6..eb309c42e6 100644 --- a/src/arch/amdgpu/gcn3/SConscript +++ b/src/arch/amdgpu/gcn3/SConscript @@ -39,15 +39,11 @@ if not env['BUILD_GPU']: Return() if env['TARGET_GPU_ISA'] == 'gcn3': - SimObject('X86GPUTLB.py', sim_objects=['X86GPUTLB', 'TLBCoalescer']) - Source('decoder.cc') Source('insts/gpu_static_inst.cc') Source('insts/instructions.cc') Source('insts/op_encodings.cc') Source('isa.cc') Source('registers.cc') - Source('tlb.cc') - Source('tlb_coalescer.cc') DebugFlag('GCN3', 'Debug flag for GCN3 GPU ISA') diff --git a/src/arch/amdgpu/gcn3/gpu_isa.hh b/src/arch/amdgpu/gcn3/gpu_isa.hh index 205f097c4b..26cbc5c3e8 100644 --- a/src/arch/amdgpu/gcn3/gpu_isa.hh +++ b/src/arch/amdgpu/gcn3/gpu_isa.hh @@ -37,8 +37,8 @@ #include #include +#include "arch/amdgpu/common/tlb.hh" #include "arch/amdgpu/gcn3/gpu_registers.hh" -#include "arch/amdgpu/gcn3/tlb.hh" #include "gpu-compute/dispatcher.hh" #include "gpu-compute/hsa_queue_entry.hh" #include "gpu-compute/misc.hh" diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc index feef552bf2..761d37b672 100644 --- a/src/gpu-compute/compute_unit.cc +++ b/src/gpu-compute/compute_unit.cc @@ -35,6 +35,7 @@ #include +#include "arch/amdgpu/common/tlb.hh" #include "base/output.hh" #include "debug/GPUDisp.hh" #include "debug/GPUExec.hh" diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc index 437a48daac..fed9cb5501 100644 --- a/src/gpu-compute/fetch_unit.cc +++ b/src/gpu-compute/fetch_unit.cc @@ -33,6 +33,7 @@ #include "gpu-compute/fetch_unit.hh" +#include "arch/amdgpu/common/tlb.hh" #include "base/bitfield.hh" #include "debug/GPUFetch.hh" #include "debug/GPUPort.hh" diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc index ad18d01734..4d71ca0959 100644 --- a/src/gpu-compute/shader.cc +++ b/src/gpu-compute/shader.cc @@ -35,6 +35,7 @@ #include +#include "arch/amdgpu/common/tlb.hh" #include "base/chunk_generator.hh" #include "debug/GPUAgentDisp.hh" #include "debug/GPUDisp.hh"