diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index da78561387..f50144e1e7 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -128,11 +128,17 @@ let {{
     def vectorElem(idx, elem):
         return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
 
-    def vectorReg(idx, elems = None):
-        return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
-
-    def vectorRegElem(elem, ext = 'sf'):
-        return (elem, ext)
+    def vectorReg(idx, base, suffix = ''):
+        elems = {
+            base + 'P0' + suffix : ('0', 'sf'),
+            base + 'P1' + suffix : ('1', 'sf'),
+            base + 'P2' + suffix : ('2', 'sf'),
+            base + 'P3' + suffix : ('3', 'sf'),
+            base + 'S' + suffix : ('0', 'sf'),
+            base + 'D' + suffix : ('0', 'df'),
+            base + 'Q' + suffix : ('0', 'tud')
+        }
+        return ('VecReg', 'vc', (idx, elems), 'IsVector', srtNormal)
 
     def vecPredReg(idx):
         return ('VecPredReg', 'pc', idx, None, srtNormal)
@@ -348,281 +354,33 @@ def operands {{
     # All the constituents are hierarchically defined as part of the Vector
     # Register they belong to
 
-    'AA64FpOp1':       vectorReg('op1',
-    {
-        'AA64FpOp1P0': vectorRegElem('0'),
-        'AA64FpOp1P1': vectorRegElem('1'),
-        'AA64FpOp1P2': vectorRegElem('2'),
-        'AA64FpOp1P3': vectorRegElem('3'),
-        'AA64FpOp1S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1D':  vectorRegElem('0', 'df'),
-        'AA64FpOp1Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp2':       vectorReg('op2',
-    {
-        'AA64FpOp2P0': vectorRegElem('0'),
-        'AA64FpOp2P1': vectorRegElem('1'),
-        'AA64FpOp2P2': vectorRegElem('2'),
-        'AA64FpOp2P3': vectorRegElem('3'),
-        'AA64FpOp2S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp2D':  vectorRegElem('0', 'df'),
-        'AA64FpOp2Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp3':       vectorReg('op3',
-    {
-        'AA64FpOp3P0': vectorRegElem('0'),
-        'AA64FpOp3P1': vectorRegElem('1'),
-        'AA64FpOp3P2': vectorRegElem('2'),
-        'AA64FpOp3P3': vectorRegElem('3'),
-        'AA64FpOp3S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp3D':  vectorRegElem('0', 'df'),
-        'AA64FpOp3Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDest':       vectorReg('dest',
-    {
-        'AA64FpDestP0': vectorRegElem('0'),
-        'AA64FpDestP1': vectorRegElem('1'),
-        'AA64FpDestP2': vectorRegElem('2'),
-        'AA64FpDestP3': vectorRegElem('3'),
-        'AA64FpDestS':  vectorRegElem('0', 'sf'),
-        'AA64FpDestD':  vectorRegElem('0', 'df'),
-        'AA64FpDestQ':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDest2':       vectorReg('dest2',
-    {
-        'AA64FpDest2P0': vectorRegElem('0'),
-        'AA64FpDest2P1': vectorRegElem('1'),
-        'AA64FpDest2P2': vectorRegElem('2'),
-        'AA64FpDest2P3': vectorRegElem('3'),
-        'AA64FpDest2S':  vectorRegElem('0', 'sf'),
-        'AA64FpDest2D':  vectorRegElem('0', 'df'),
-        'AA64FpDest2Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V0':       vectorReg('op1',
-    {
-        'AA64FpOp1P0V0': vectorRegElem('0'),
-        'AA64FpOp1P1V0': vectorRegElem('1'),
-        'AA64FpOp1P2V0': vectorRegElem('2'),
-        'AA64FpOp1P3V0': vectorRegElem('3'),
-        'AA64FpOp1SV0':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV0':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV0':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V1':       vectorReg('op1+1',
-    {
-        'AA64FpOp1P0V1': vectorRegElem('0'),
-        'AA64FpOp1P1V1': vectorRegElem('1'),
-        'AA64FpOp1P2V1': vectorRegElem('2'),
-        'AA64FpOp1P3V1': vectorRegElem('3'),
-        'AA64FpOp1SV1':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV1':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV1':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V2':       vectorReg('op1+2',
-    {
-        'AA64FpOp1P0V2': vectorRegElem('0'),
-        'AA64FpOp1P1V2': vectorRegElem('1'),
-        'AA64FpOp1P2V2': vectorRegElem('2'),
-        'AA64FpOp1P3V2': vectorRegElem('3'),
-        'AA64FpOp1SV2':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV2':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV2':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V3':       vectorReg('op1+3',
-    {
-        'AA64FpOp1P0V3': vectorRegElem('0'),
-        'AA64FpOp1P1V3': vectorRegElem('1'),
-        'AA64FpOp1P2V3': vectorRegElem('2'),
-        'AA64FpOp1P3V3': vectorRegElem('3'),
-        'AA64FpOp1SV3':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV3':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV3':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V0S':       vectorReg('(op1+0)%32',
-    {
-        'AA64FpOp1P0V0S': vectorRegElem('0'),
-        'AA64FpOp1P1V0S': vectorRegElem('1'),
-        'AA64FpOp1P2V0S': vectorRegElem('2'),
-        'AA64FpOp1P3V0S': vectorRegElem('3'),
-        'AA64FpOp1SV0S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV0S':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV0S':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V1S':       vectorReg('(op1+1)%32',
-    {
-        'AA64FpOp1P0V1S': vectorRegElem('0'),
-        'AA64FpOp1P1V1S': vectorRegElem('1'),
-        'AA64FpOp1P2V1S': vectorRegElem('2'),
-        'AA64FpOp1P3V1S': vectorRegElem('3'),
-        'AA64FpOp1SV1S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV1S':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV1S':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V2S':       vectorReg('(op1+2)%32',
-    {
-        'AA64FpOp1P0V2S': vectorRegElem('0'),
-        'AA64FpOp1P1V2S': vectorRegElem('1'),
-        'AA64FpOp1P2V2S': vectorRegElem('2'),
-        'AA64FpOp1P3V2S': vectorRegElem('3'),
-        'AA64FpOp1SV2S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV2S':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV2S':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOp1V3S':       vectorReg('(op1+3)%32',
-    {
-        'AA64FpOp1P0V3S': vectorRegElem('0'),
-        'AA64FpOp1P1V3S': vectorRegElem('1'),
-        'AA64FpOp1P2V3S': vectorRegElem('2'),
-        'AA64FpOp1P3V3S': vectorRegElem('3'),
-        'AA64FpOp1SV3S':  vectorRegElem('0', 'sf'),
-        'AA64FpOp1DV3S':  vectorRegElem('0', 'df'),
-        'AA64FpOp1QV3S':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDestV0':       vectorReg('(dest+0)',
-    {
-        'AA64FpDestP0V0': vectorRegElem('0'),
-        'AA64FpDestP1V0': vectorRegElem('1'),
-        'AA64FpDestP2V0': vectorRegElem('2'),
-        'AA64FpDestP3V0': vectorRegElem('3'),
-        'AA64FpDestSV0':  vectorRegElem('0', 'sf'),
-        'AA64FpDestDV0':  vectorRegElem('0', 'df'),
-        'AA64FpDestQV0':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDestV1':       vectorReg('(dest+1)',
-    {
-        'AA64FpDestP0V1': vectorRegElem('0'),
-        'AA64FpDestP1V1': vectorRegElem('1'),
-        'AA64FpDestP2V1': vectorRegElem('2'),
-        'AA64FpDestP3V1': vectorRegElem('3'),
-        'AA64FpDestSV1':  vectorRegElem('0', 'sf'),
-        'AA64FpDestDV1':  vectorRegElem('0', 'df'),
-        'AA64FpDestQV1':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDestV0L':       vectorReg('(dest+0)%32',
-    {
-        'AA64FpDestP0V0L': vectorRegElem('0'),
-        'AA64FpDestP1V0L': vectorRegElem('1'),
-        'AA64FpDestP2V0L': vectorRegElem('2'),
-        'AA64FpDestP3V0L': vectorRegElem('3'),
-        'AA64FpDestSV0L':  vectorRegElem('0', 'sf'),
-        'AA64FpDestDV0L':  vectorRegElem('0', 'df'),
-        'AA64FpDestQV0L':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDestV1L':       vectorReg('(dest+1)%32',
-    {
-        'AA64FpDestP0V1L': vectorRegElem('0'),
-        'AA64FpDestP1V1L': vectorRegElem('1'),
-        'AA64FpDestP2V1L': vectorRegElem('2'),
-        'AA64FpDestP3V1L': vectorRegElem('3'),
-        'AA64FpDestSV1L':  vectorRegElem('0', 'sf'),
-        'AA64FpDestDV1L':  vectorRegElem('0', 'df'),
-        'AA64FpDestQV1L':  vectorRegElem('0', 'tud')
-    }),
+    'AA64FpOp1': vectorReg('op1', 'AA64FpOp1'),
+    'AA64FpOp2': vectorReg('op2', 'AA64FpOp2'),
+    'AA64FpOp3': vectorReg('op3', 'AA64FpOp3'),
+    'AA64FpDest': vectorReg('dest', 'AA64FpDest'),
+    'AA64FpDest2': vectorReg('dest2', 'AA64FpDest2'),
+    'AA64FpOp1V0': vectorReg('op1', 'AA64FpOp1', 'V0'),
+    'AA64FpOp1V1': vectorReg('op1 + 1', 'AA64FpOp1', 'V1'),
+    'AA64FpOp1V2': vectorReg('op1 + 2', 'AA64FpOp1', 'V2'),
+    'AA64FpOp1V3': vectorReg('op1 + 3', 'AA64FpOp1', 'V3'),
+    'AA64FpOp1V0S': vectorReg('(op1 + 0) % 32', 'AA64FpOp1', 'V0S'),
+    'AA64FpOp1V1S': vectorReg('(op1 + 1) % 32', 'AA64FpOp1', 'V1S'),
+    'AA64FpOp1V2S': vectorReg('(op1 + 2) % 32', 'AA64FpOp1', 'V2S'),
+    'AA64FpOp1V3S': vectorReg('(op1 + 3) % 32', 'AA64FpOp1', 'V3S'),
+    'AA64FpDestV0': vectorReg('(dest + 0)', 'AA64FpDest', 'V0'),
+    'AA64FpDestV1': vectorReg('(dest + 1)', 'AA64FpDest', 'V1'),
+    'AA64FpDestV0L': vectorReg('(dest + 0) % 32', 'AA64FpDest', 'V0L'),
+    'AA64FpDestV1L': vectorReg('(dest + 1) % 32', 'AA64FpDest', 'V1L'),
 
     # Temporary registers for SVE interleaving
-    'AA64IntrlvReg0': vectorReg('INTRLVREG0',
-    {
-        'AA64IntrlvReg0P0': vectorRegElem('0'),
-        'AA64IntrlvReg0P1': vectorRegElem('1'),
-        'AA64IntrlvReg0P2': vectorRegElem('2'),
-        'AA64IntrlvReg0P3': vectorRegElem('3'),
-        'AA64IntrlvReg0S':  vectorRegElem('0', 'sf'),
-        'AA64IntrlvReg0D':  vectorRegElem('0', 'df'),
-        'AA64IntrlvReg0Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64IntrlvReg1': vectorReg('INTRLVREG1',
-    {
-        'AA64IntrlvReg1P0': vectorRegElem('0'),
-        'AA64IntrlvReg1P1': vectorRegElem('1'),
-        'AA64IntrlvReg1P2': vectorRegElem('2'),
-        'AA64IntrlvReg1P3': vectorRegElem('3'),
-        'AA64IntrlvReg1S':  vectorRegElem('0', 'sf'),
-        'AA64IntrlvReg1D':  vectorRegElem('0', 'df'),
-        'AA64IntrlvReg1Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64IntrlvReg2': vectorReg('INTRLVREG2',
-    {
-        'AA64IntrlvReg2P0': vectorRegElem('0'),
-        'AA64IntrlvReg2P1': vectorRegElem('1'),
-        'AA64IntrlvReg2P2': vectorRegElem('2'),
-        'AA64IntrlvReg2P3': vectorRegElem('3'),
-        'AA64IntrlvReg2S':  vectorRegElem('0', 'sf'),
-        'AA64IntrlvReg2D':  vectorRegElem('0', 'df'),
-        'AA64IntrlvReg2Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64IntrlvReg3': vectorReg('INTRLVREG3',
-    {
-        'AA64IntrlvReg3P0': vectorRegElem('0'),
-        'AA64IntrlvReg3P1': vectorRegElem('1'),
-        'AA64IntrlvReg3P2': vectorRegElem('2'),
-        'AA64IntrlvReg3P3': vectorRegElem('3'),
-        'AA64IntrlvReg3S':  vectorRegElem('0', 'sf'),
-        'AA64IntrlvReg3D':  vectorRegElem('0', 'df'),
-        'AA64IntrlvReg3Q':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpDestMerge':       vectorReg('dest',
-    {
-        'AA64FpDestMergeP0': vectorRegElem('0'),
-        'AA64FpDestMergeP1': vectorRegElem('1'),
-        'AA64FpDestMergeP2': vectorRegElem('2'),
-        'AA64FpDestMergeP3': vectorRegElem('3'),
-        'AA64FpDestMergeS':  vectorRegElem('0', 'sf'),
-        'AA64FpDestMergeD':  vectorRegElem('0', 'df'),
-        'AA64FpDestMergeQ':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpBase': vectorReg('base',
-    {
-        'AA64FpBaseP0': vectorRegElem('0'),
-        'AA64FpBaseP1': vectorRegElem('1'),
-        'AA64FpBaseP2': vectorRegElem('2'),
-        'AA64FpBaseP3': vectorRegElem('3'),
-        'AA64FpBaseS':  vectorRegElem('0', 'sf'),
-        'AA64FpBaseD':  vectorRegElem('0', 'df'),
-        'AA64FpBaseQ':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpOffset': vectorReg('offset',
-    {
-        'AA64FpOffsetP0': vectorRegElem('0'),
-        'AA64FpOffsetP1': vectorRegElem('1'),
-        'AA64FpOffsetP2': vectorRegElem('2'),
-        'AA64FpOffsetP3': vectorRegElem('3'),
-        'AA64FpOffsetS':  vectorRegElem('0', 'sf'),
-        'AA64FpOffsetD':  vectorRegElem('0', 'df'),
-        'AA64FpOffsetQ':  vectorRegElem('0', 'tud')
-    }),
-
-    'AA64FpUreg0': vectorReg('VECREG_UREG0',
-    {
-        'AA64FpUreg0P0': vectorRegElem('0'),
-        'AA64FpUreg0P1': vectorRegElem('1'),
-        'AA64FpUreg0P2': vectorRegElem('2'),
-        'AA64FpUreg0P3': vectorRegElem('3'),
-        'AA64FpUreg0S':  vectorRegElem('0', 'sf'),
-        'AA64FpUreg0D':  vectorRegElem('0', 'df'),
-        'AA64FpUreg0Q':  vectorRegElem('0', 'tud')
-    }),
+    'AA64IntrlvReg0': vectorReg('INTRLVREG0', 'AA64FpIntrlvReg0'),
+    'AA64IntrlvReg1': vectorReg('INTRLVREG1', 'AA64FpIntrlvReg1'),
+    'AA64IntrlvReg2': vectorReg('INTRLVREG2', 'AA64FpIntrlvReg2'),
+    'AA64IntrlvReg3': vectorReg('INTRLVREG3', 'AA64FpIntrlvReg3'),
+    'AA64FpDestMerge': vectorReg('dest', 'AA64FpDestMerge'),
+    'AA64FpBase': vectorReg('base', 'AA64FpBase'),
+    'AA64FpOffset': vectorReg('offset', 'AA64FpOffset'),
+    'AA64FpUreg0': vectorReg('VECREG_UREG0', 'AA64FpUreg0'),
 
     # Predicate register operands
     'GpOp': vecPredReg('gp'),