Mem: Change isLlsc to isLLSC.
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4
src/mem/cache/cache_impl.hh
vendored
4
src/mem/cache/cache_impl.hh
vendored
@@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk)
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pkt->writeDataToBlock(blk->data, blkSize);
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}
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} else if (pkt->isRead()) {
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if (pkt->isLlsc()) {
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if (pkt->isLLSC()) {
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blk->trackLoadLocked(pkt);
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}
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pkt->setDataFromBlock(blk->data, blkSize);
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@@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
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incMissCount(pkt);
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if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) {
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if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
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// complete miss on store conditional... just give up now
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pkt->req->setExtraData(0);
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return true;
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