Mem: Change isLlsc to isLLSC.

src/mem/cache/blk.hh

@@ -218,7 +218,7 @@ class CacheBlk
      */
     void trackLoadLocked(PacketPtr pkt)
     {
-        assert(pkt->isLlsc());
+        assert(pkt->isLLSC());
         lockList.push_front(Lock(pkt->req));
     }
 
@@ -236,7 +236,7 @@ class CacheBlk
     bool checkWrite(PacketPtr pkt)
     {
         Request *req = pkt->req;
-        if (pkt->isLlsc()) {
+        if (pkt->isLLSC()) {
             // it's a store conditional... have to check for matching
             // load locked.
             bool success = false;

src/mem/cache/cache_impl.hh

@@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk)
             pkt->writeDataToBlock(blk->data, blkSize);
         }
     } else if (pkt->isRead()) {
-        if (pkt->isLlsc()) {
+        if (pkt->isLLSC()) {
             blk->trackLoadLocked(pkt);
         }
         pkt->setDataFromBlock(blk->data, blkSize);
@@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
 
     incMissCount(pkt);
 
-    if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) {
+    if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
         // complete miss on store conditional... just give up now
         pkt->req->setExtraData(0);
         return true;