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Mem: Change isLlsc to isLLSC.

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This commit is contained in:
Gabe Black
2009-04-19 21:44:15 -07:00
parent 089b384086
commit bd6f2bb538
17 changed files with 43 additions and 43 deletions
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6
src/cpu/inorder/resources/cache_unit.cc
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@@ -355,7 +355,7 @@ CacheUnit::doDataAccess(DynInstPtr inst)
Request *memReq = cache_req->dataPkt->req;
if (cache_req->dataPkt->isWrite() && memReq->isLlsc()) {
if (cache_req->dataPkt->isWrite() && memReq->isLLSC()) {
assert(cache_req->inst->isStoreConditional());
DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
do_access = TheISA::handleLockedWrite(cpu, memReq);
@@ -395,7 +395,7 @@ CacheUnit::doDataAccess(DynInstPtr inst)
cacheStatus = cacheWaitResponse;
cacheBlocked = false;
}
} else if (!do_access && memReq->isLlsc()){
} else if (!do_access && memReq->isLLSC()){
// Store-Conditional instructions complete even if they "failed"
assert(cache_req->inst->isStoreConditional());
cache_req->setCompleted(true);
@@ -471,7 +471,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
if (inst->isLoad()) {
assert(cache_pkt->isRead());
if (cache_pkt->req->isLlsc()) {
if (cache_pkt->req->isLLSC()) {
DPRINTF(InOrderCachePort,
"[tid:%u]: Handling Load-Linked for [sn:%u]\n",
tid, inst->seqNum);