diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c8b752c914..f49a2a87d7 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -575,3 +575,17 @@ ISA::globalClearExclusive()
 
 } // namespace RiscvISA
 } // namespace gem5
+
+std::ostream &
+operator<<(std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)
+{
+    switch (pm) {
+    case gem5::RiscvISA::PRV_U:
+        return os << "PRV_U";
+    case gem5::RiscvISA::PRV_S:
+        return os << "PRV_S";
+    case gem5::RiscvISA::PRV_M:
+        return os << "PRV_M";
+    }
+    return os << "PRV_<invalid>";
+}
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 143cc698a6..81923b5aef 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -119,4 +119,6 @@ class ISA : public BaseISA
 } // namespace RiscvISA
 } // namespace gem5
 
+std::ostream &operator<<(std::ostream &os, gem5::RiscvISA::PrivilegeMode pm);
+
 #endif // __ARCH_RISCV_ISA_HH__