From bc9e90d65e3c2813d2eed70b45abd7c62702851c Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Tue, 3 Jan 2023 11:40:45 -0800 Subject: [PATCH] arch-vega: Make VGPR-offset for global SGPR-base signed The VGPR-offset used when SGPR-base addressing is used can be signed in Vega. These are global instructions of the format: `global_load_dword v0, v1, s[0:1]`. This is not explicitly stated in the ISA manual however based on compiler output the offset can be negative. This changeset assigns the offset to a signed 32-bit integer and the compiler takes care of the signedness in the expression which calculates the final address. This fixes a bad address calculation in a rocPRIM unit test. Change-Id: I271edfbb4c6344cb1a6a69a0fd3df58a6198d599 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67412 Reviewed-by: Bobby Bruce Maintainer: Bobby Bruce Tested-by: kokoro --- src/arch/amdgpu/vega/insts/op_encodings.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh b/src/arch/amdgpu/vega/insts/op_encodings.hh index 34f6040495..1071eada0e 100644 --- a/src/arch/amdgpu/vega/insts/op_encodings.hh +++ b/src/arch/amdgpu/vega/insts/op_encodings.hh @@ -1007,8 +1007,9 @@ namespace VegaISA // mask any upper bits from the vaddr. for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) { if (gpuDynInst->exec_mask[lane]) { + ScalarRegI32 voffset = vaddr[lane]; gpuDynInst->addr.at(lane) = - saddr.rawData() + (vaddr[lane] & 0xffffffff) + offset; + saddr.rawData() + voffset + offset; } } }