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arch-vega: Add VOP3P encodings and packed 16b insts

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This adds the VOP3P and VOP3P_MAI encodings from the MI200 spec. These
instructions are used for packed math and miSIMD instructions. The first
19 VOP3P opcodes are implemented and validated against hardware. This
includes all instructions which operate on one dword containing two
packed 16-bit values of fp16, int16_t, or uint16_t.

Implement one MFMA instruction for now which was also validated against
hardware.
This commit is contained in:
Matthew Poremba
2023-12-08 12:34:23 -06:00
parent 4903fe2db1
commit bc69ab0a1f
9 changed files with 1183 additions and 41 deletions
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26
src/arch/amdgpu/vega/gpu_decoder.hh
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@@ -1585,6 +1585,8 @@ namespace VegaISA
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIX_F32(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_PK_MOV_B32(MachInst);
GPUStaticInst* decode_OP_VOP3P__V_MFMA_F64_16X16X4F64(MachInst);
GPUStaticInst* subDecode_OPU_VOP3(MachInst);
GPUStaticInst* subDecode_OP_DS(MachInst);
GPUStaticInst* subDecode_OP_FLAT(MachInst);
@@ -1908,7 +1910,27 @@ namespace VegaISA
unsigned int NEG : 3;
};
union InstFormat {
struct InFmt_VOP3P_MAI
{
unsigned int VDST : 8;
unsigned int CBSZ : 3;
unsigned int ABID : 4;
unsigned int ACC_CD : 1;
unsigned int OP : 7;
unsigned int ENCODING : 9;
};
struct InFmt_VOP3P_MAI_1
{
unsigned int SRC0 : 9;
unsigned int SRC1 : 9;
unsigned int SRC2 : 9;
unsigned int ACC : 2;
unsigned int BLGP : 3;
};
union InstFormat
{
InFmt_DS iFmt_DS;
InFmt_DS_1 iFmt_DS_1;
InFmt_EXP iFmt_EXP;
@@ -1941,6 +1963,8 @@ namespace VegaISA
InFmt_VOP_SDWAB iFmt_VOP_SDWAB;
InFmt_VOP3P iFmt_VOP3P;
InFmt_VOP3P_1 iFmt_VOP3P_1;
InFmt_VOP3P_MAI iFmt_VOP3P_MAI;
InFmt_VOP3P_MAI_1 iFmt_VOP3P_MAI_1;
uint32_t imm_u32;
float imm_f32;
}; // union InstFormat