mem: Add DRAMSys wrapper as a memory object

Add a DRAMSys wrapper to the gem5 memory source that
instantiates the DRAMSys simulator.
Another DRAMSys SimObject implements the AbstractMemory
interface and exposes the tlm target socket.

Change-Id: I8a95e729905e0924453043e5e7744df7a7ce4548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62912
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>

ext/dramsys/SConscript

@@ -1,32 +1,28 @@
-# Copyright (c) 2022, Fraunhofer IESE
+# Copyright (c) 2022 Fraunhofer IESE
-# All rights reserved.
+# All rights reserved
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
-# met:
+# met: redistributions of source code must retain the above copyright
-#
+# notice, this list of conditions and the following disclaimer;
-# 1. Redistributions of source code must retain the above copyright notice,
+# redistributions in binary form must reproduce the above copyright
-#    this list of conditions and the following disclaimer.
+# notice, this list of conditions and the following disclaimer in the
-#
+# documentation and/or other materials provided with the distribution;
-# 2. Redistributions in binary form must reproduce the above copyright
+# neither the name of the copyright holders nor the names of its
-#    notice, this list of conditions and the following disclaimer in the
+# contributors may be used to endorse or promote products derived from
-#    documentation and/or other materials provided with the distribution.
+# this software without specific prior written permission.
-#
-# 3. Neither the name of the copyright holder nor the names of its
-#    contributors may be used to endorse or promote products derived from
-#    this software without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import os
 

src/mem/DRAMSys.py

@@ -0,0 +1,43 @@
+# Copyright (c) 2022 Fraunhofer IESE
+# All rights reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import *
+from m5.params import *
+from m5.proxy import *
+
+from m5.objects.Tlm import TlmTargetSocket
+from m5.objects.AbstractMemory import *
+
+
+class DRAMSys(AbstractMemory):
+    type = "DRAMSys"
+    cxx_class = "gem5::memory::DRAMSys"
+    cxx_header = "mem/dramsys.hh"
+    tlm = TlmTargetSocket(32, "TLM target port")
+
+    configuration = Param.String("Path to the DRAMSys configuration")
+    resource_directory = Param.String("Path to the DRAMSys resource directory")
+    recordable = Param.Bool(True, "Whether DRAMSys should record a trace file")

src/mem/SConscript

@@ -121,6 +121,10 @@ if env['HAVE_DRAMSIM3']:
     Source('dramsim3_wrapper.cc')
     Source('dramsim3.cc')
 
+if env['HAVE_DRAMSYS']:
+    SimObject('DRAMSys.py', sim_objects=['DRAMSys'])
+    Source('dramsys_wrapper.cc')
+
 SimObject('MemChecker.py', sim_objects=['MemChecker', 'MemCheckerMonitor'])
 Source('mem_checker.cc')
 Source('mem_checker_monitor.cc')

src/mem/dramsys.hh

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022 Fraunhofer IESE
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_DRAMSYS_H__
+#define __MEM_DRAMSYS_H__
+
+#include "DRAMSysConfiguration.h"
+#include "mem/abstract_mem.hh"
+#include "mem/dramsys_wrapper.hh"
+#include "params/DRAMSys.hh"
+
+namespace gem5
+{
+
+namespace memory
+{
+
+class DRAMSys : public AbstractMemory
+{
+    PARAMS(DRAMSys);
+    sc_gem5::TlmTargetWrapper<32> tlmWrapper;
+
+  public:
+    DRAMSys(Params const &params)
+        : AbstractMemory(params),
+          tlmWrapper(dramSysWrapper.tSocket,
+              params.name + ".tlm",
+              InvalidPortID),
+          config(DRAMSysConfiguration::from_path(
+              params.configuration,
+              params.resource_directory)),
+          dramSysWrapper(params.name.c_str(),
+            config,
+            params.recordable,
+            params.range)
+    {
+    }
+
+    gem5::Port &getPort(const std::string &if_name, PortID idx) override
+    {
+        if (if_name != "tlm")
+        {
+            return AbstractMemory::getPort(if_name, idx);
+        }
+
+        return tlmWrapper;
+    }
+
+  private:
+    DRAMSysConfiguration::Configuration config;
+    DRAMSysWrapper dramSysWrapper;
+};
+
+} // namespace memory
+} // namespace gem5
+
+#endif // __MEM_DRAMSYS_HH__

src/mem/dramsys_wrapper.cc

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2022 Fraunhofer IESE
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dramsys_wrapper.hh"
+
+namespace gem5
+{
+
+namespace memory
+{
+
+DRAMSysWrapper::DRAMSysWrapper(
+    sc_core::sc_module_name name,
+    DRAMSysConfiguration::Configuration const &config,
+    bool recordable,
+    AddrRange range) :
+    sc_core::sc_module(name),
+    dramsys(instantiateDRAMSys(recordable, config)),
+    range(range)
+{
+    tSocket.register_nb_transport_fw(this, &DRAMSysWrapper::nb_transport_fw);
+    tSocket.register_transport_dbg(this, &DRAMSysWrapper::transport_dbg);
+    iSocket.register_nb_transport_bw(this, &DRAMSysWrapper::nb_transport_bw);
+    iSocket.bind(dramsys->tSocket);
+
+    // Register a callback to compensate for the destructor not
+    // being called.
+    registerExitCallback(
+        [this]()
+        {
+            // Workaround for BUG GEM5-1233
+            sc_gem5::Kernel::stop();
+        });
+}
+
+std::shared_ptr<::DRAMSys>
+DRAMSysWrapper::instantiateDRAMSys(
+    bool recordable,
+    DRAMSysConfiguration::Configuration const &config)
+{
+    return recordable
+        ? std::make_shared<::DRAMSysRecordable>("DRAMSys", config)
+        : std::make_shared<::DRAMSys>("DRAMSys", config);
+}
+
+tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_fw(
+    tlm::tlm_generic_payload &payload,
+    tlm::tlm_phase &phase,
+    sc_core::sc_time &fwDelay)
+{
+    // Subtract base address offset
+    payload.set_address(payload.get_address() - range.start());
+
+    return iSocket->nb_transport_fw(payload, phase, fwDelay);
+}
+
+tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_bw(
+    tlm::tlm_generic_payload &payload,
+    tlm::tlm_phase &phase,
+    sc_core::sc_time &bwDelay)
+{
+    return tSocket->nb_transport_bw(payload, phase, bwDelay);
+}
+
+unsigned int DRAMSysWrapper::transport_dbg(tlm::tlm_generic_payload &trans)
+{
+    // Subtract base address offset
+    trans.set_address(trans.get_address() - range.start());
+
+    return iSocket->transport_dbg(trans);
+}
+
+} // namespace memory
+} // namespace gem5

src/mem/dramsys_wrapper.hh

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2022 Fraunhofer IESE
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_DRAMSYS_WRAPPER_HH__
+#define __MEM_DRAMSYS_WRAPPER_HH__
+
+#include <iostream>
+#include <memory>
+
+#include "DRAMSysConfiguration.h"
+#include "params/DRAMSys.hh"
+#include "sim/core.hh"
+#include "simulation/DRAMSysRecordable.h"
+#include "systemc/core/kernel.hh"
+#include "systemc/ext/core/sc_module_name.hh"
+#include "systemc/ext/systemc"
+#include "systemc/ext/tlm"
+#include "systemc/ext/tlm_utils/simple_target_socket.h"
+#include "systemc/tlm_port_wrapper.hh"
+
+namespace gem5
+{
+
+namespace memory
+{
+
+class DRAMSysWrapper : public sc_core::sc_module
+{
+    friend class DRAMSys;
+
+  public:
+    SC_HAS_PROCESS(DRAMSysWrapper);
+    DRAMSysWrapper(sc_core::sc_module_name name,
+                   DRAMSysConfiguration::Configuration const &config,
+                   bool recordable,
+                   AddrRange range);
+
+  private:
+    static std::shared_ptr<::DRAMSys>
+    instantiateDRAMSys(bool recordable,
+        DRAMSysConfiguration::Configuration const &config);
+
+    tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
+                                       tlm::tlm_phase &phase,
+                                       sc_core::sc_time &fwDelay);
+
+    tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload,
+                                       tlm::tlm_phase &phase,
+                                       sc_core::sc_time &bwDelay);
+
+    unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
+
+    tlm_utils::simple_initiator_socket<DRAMSysWrapper> iSocket;
+    tlm_utils::simple_target_socket<DRAMSysWrapper> tSocket;
+
+    std::shared_ptr<::DRAMSys> dramsys;
+
+    AddrRange range;
+};
+
+} // namespace memory
+} // namespace gem5
+
+#endif // __MEM_DRAMSYS_WRAPPER_HH__

src/python/gem5/components/memory/dramsys.py

@@ -0,0 +1,89 @@
+# Copyright (c) 2022 Fraunhofer IESE
+# All rights reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import m5
+import os
+import configparser
+
+from m5.objects import DRAMSys, AddrRange, Port, MemCtrl, Gem5ToTlmBridge32
+from m5.util.convert import toMemorySize
+
+from ...utils.override import overrides
+from ..boards.abstract_board import AbstractBoard
+from .abstract_memory_system import AbstractMemorySystem
+
+from typing import Optional, Tuple, Sequence, List
+
+
+class DRAMSysMem(AbstractMemorySystem):
+    def __init__(
+        self,
+        configuration: str,
+        size: str,
+        resource_directory: str,
+        recordable: bool,
+    ) -> None:
+        """
+        :param configuration: Path to the base configuration JSON for DRAMSys.
+        :param size: Memory size of DRAMSys. Must match the size specified in JSON configuration.
+        :param resource_directory: Path to the base resource directory for DRAMSys.
+        :param recordable: Whether the database recording feature of DRAMSys is enabled.
+        """
+        super().__init__()
+        self.dramsys = DRAMSys(
+            configuration=configuration,
+            resource_directory=resource_directory,
+            recordable=recordable,
+        )
+
+        self._size = toMemorySize(size)
+        self._bridge = Gem5ToTlmBridge32()
+        self.dramsys.port = self._bridge.tlm
+
+    @overrides(AbstractMemorySystem)
+    def incorporate_memory(self, board: AbstractBoard) -> None:
+        pass
+
+    @overrides(AbstractMemorySystem)
+    def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+        return [(self.dramsys.range, self._bridge.gem5)]
+
+    @overrides(AbstractMemorySystem)
+    def get_memory_controllers(self) -> List[MemCtrl]:
+        return [self.dramsys]
+
+    @overrides(AbstractMemorySystem)
+    def get_size(self) -> int:
+        return self._size
+
+    @overrides(AbstractMemorySystem)
+    def set_memory_range(self, ranges: List[AddrRange]) -> None:
+        if len(ranges) != 1 or ranges[0].size() != self._size:
+            raise Exception(
+                "DRAMSys memory controller requires a single "
+                "range which matches the memory's size."
+            )
+        self.dramsys.range = ranges[0]