diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py b/configs/example/gem5_library/riscv-ubuntu-run.py
index f558b8df72..ef82b53801 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -49,9 +49,8 @@ from gem5.components.memory import DualChannelDDR4_2400
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource
 from gem5.simulate.simulator import Simulator
+from gem5.resource.workload import Workload
 
 # This runs a check to ensure the gem5 binary is compiled for RISCV.
 
@@ -85,23 +84,11 @@ board = RiscvBoard(
     cache_hierarchy=cache_hierarchy,
 )
 
-# Here we set the Full System workload.
-
-# The `set_kernel_disk_workload` function for the RiscvBoard accepts a
-# RISCV bootloader and a disk image. Once the system successfully boots, it
-# encounters an `m5_exit instruction encountered`. We stop the simulation then.
-# When the simulation has ended you may inspect `m5out/system.pc.com_1.device`
-# to see the stdout.
-
-board.set_kernel_disk_workload(
-    # The RISCV bootloader will be automatically downloaded to the
-    # `~/.cache/gem5` directory if not already present.
-    # The riscv-ubuntu boot-test was tested with riscv-bootloader-5.10
-    kernel=Resource("riscv-bootloader-vmlinux-5.10"),
-    # The RISCV ubuntu image will be automatically downloaded to the
-    # `~/.cache/gem5` directory if not already present.
-    disk_image=Resource("riscv-ubuntu-20.04-img"),
-)
+# Here we a full system workload: "riscv-ubuntu-20.04-boot" which boots
+# Ubuntu 20.04. Once the system successfully boots it encounters an `m5_exit`
+# instruction which stops the simulation. When the simulation has ended you may
+# inspect `m5out/system.pc.com_1.device` to see the stdout.
+board.set_workload(Workload("riscv-ubuntu-20.04-boot"))
 
 simulator = Simulator(board=board)
 simulator.run()
diff --git a/tests/gem5/configs/riscv_boot_exit_run.py b/tests/gem5/configs/riscv_boot_exit_run.py
index 9931ba0516..1636fac5a6 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -40,6 +40,7 @@ from gem5.components.processors.cpu_types import CPUTypes
 from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.processors.simple_processor import SimpleProcessor
 from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
 
 import argparse
 import importlib
@@ -150,16 +151,12 @@ board = RiscvBoard(
     cache_hierarchy=cache_hierarchy,
 )
 
-# Set the Full System workload.
-board.set_kernel_disk_workload(
-    kernel=Resource(
-        "riscv-bootloader-vmlinux-5.10",
-        resource_directory=args.resource_directory,
-    ),
-    disk_image=Resource(
-        "riscv-ubuntu-20.04-img", resource_directory=args.resource_directory
-    ),
+# Set the workload.
+workload = Workload(
+    "riscv-ubuntu-20.04-boot", resource_directory=args.resource_directory
 )
+board.set_workload(workload)
+
 
 simulator = Simulator(board=board)