From 31ffc11c57caf972e21607ad48712a719ae023b6 Mon Sep 17 00:00:00 2001
From: QQeg <0909kfcmailo@gmail.com>
Date: Fri, 26 Jan 2024 13:53:59 +0000
Subject: [PATCH 1/2] arch-riscv: Fix segmentation fault in vmsbf/vmsof/vmsif

This commit simplifies the conditional logic in vmsbf/vmsof/vmsif
by removing an unnecessary variable and condition.
The updated logic checks 'this->vm' or the result of 'elem_mask(v0, i)'
directly, which prevents a segmentation fault regardless of
whether 'vm' is set or not.

Change-Id: I799fa7b684ff98959a64f9694ef9c854f3a1f43a
---
 src/arch/riscv/isa/decoder.isa | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 678e662251..d6a85d300d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -3146,12 +3146,11 @@ decode QUADRANT default Unknown::unknown() {
                         bool has_one = false;
                         for (uint32_t i = 0; i < (uint32_t)machInst.vl; i++) {
                             bool vs2_lsb = elem_mask(Vs2_vu, i);
-                            bool do_mask = elem_mask(v0, i);
-                            if(this->vm||(this->vm == 0&&do_mask)){
+                            if (this->vm || elem_mask(v0, i)){
                                 uint64_t res = 0;
                                 if (!has_one && !vs2_lsb) {
                                     res = 1;
-                                } else if(!has_one && vs2_lsb) {
+                                } else if (!has_one && vs2_lsb) {
                                     has_one = true;
                                 }
                                 Vd_ub[i/8] = ASSIGN_VD_BIT(i, res);
@@ -3162,10 +3161,9 @@ decode QUADRANT default Unknown::unknown() {
                         bool has_one = false;
                         for (uint32_t i = 0; i < (uint32_t)machInst.vl; i++) {
                             bool vs2_lsb = elem_mask(Vs2_vu, i);
-                            bool do_mask = elem_mask(v0, i);
-                            if(this->vm||(this->vm == 0&&do_mask)){
+                            if (this->vm || elem_mask(v0, i)){
                                 uint64_t res = 0;
-                                if(!has_one && vs2_lsb) {
+                                if (!has_one && vs2_lsb) {
                                     has_one = true;
                                     res = 1;
                                 }
@@ -3177,12 +3175,11 @@ decode QUADRANT default Unknown::unknown() {
                         bool has_one = false;
                         for (uint32_t i = 0; i < (uint32_t)machInst.vl; i++) {
                             bool vs2_lsb = elem_mask(Vs2_vu, i);
-                            bool do_mask = elem_mask(v0, i);
-                            if(this->vm||(this->vm == 0&&do_mask)){
+                            if (this->vm || elem_mask(v0, i)){
                                 uint64_t res = 0;
                                 if (!has_one && !vs2_lsb) {
                                     res = 1;
-                                } else if(!has_one && vs2_lsb) {
+                                } else if (!has_one && vs2_lsb) {
                                     has_one = true;
                                     res = 1;
                                 }

From 08ed87bc9d1197f9c997c4d3ca686dec8f0bd033 Mon Sep 17 00:00:00 2001
From: QQeg <0909kfcmailo@gmail.com>
Date: Fri, 26 Jan 2024 15:18:07 +0000
Subject: [PATCH 2/2] arch-riscv: Add template Vector1Vs1VdMaskDeclare

This commit adds a new template, Vector1Vs1VdMaskDeclare, to replace
the use of Vector1Vs1RdMaskDeclare in Vector1Vs1VdMaskFormat.

The change addresses the issue with the number of indices in srcRegIdxArr.
Only two indices are available in Vector1Vs1RdMaskDeclare, but instructions
that use Vector1Vs1VdMaskFormat, like 'vmsbf', require three indices
(for vs1, vs2(old_vd), and vm) to function correctly.

Change-Id: I0c966e11289ce07efcc3b0cc56948311289530ad
---
 src/arch/riscv/isa/formats/vector_arith.isa   |  2 +-
 src/arch/riscv/isa/templates/vector_arith.isa | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/arch/riscv/isa/formats/vector_arith.isa b/src/arch/riscv/isa/formats/vector_arith.isa
index 1ddf323f04..7f87f1e163 100644
--- a/src/arch/riscv/isa/formats/vector_arith.isa
+++ b/src/arch/riscv/isa/formats/vector_arith.isa
@@ -1049,7 +1049,7 @@ def format Vector1Vs1VdMaskFormat(code, category, *flags){{
          },
         flags)
 
-    header_output = Vector1Vs1RdMaskDeclare.subst(iop)
+    header_output = Vector1Vs1VdMaskDeclare.subst(iop)
     decoder_output = Vector1Vs1VdMaskConstructor.subst(iop)
     exec_output = Vector1Vs1VdMaskExecute.subst(iop)
     decode_block = VectorMaskDecodeBlock.subst(iop)
diff --git a/src/arch/riscv/isa/templates/vector_arith.isa b/src/arch/riscv/isa/templates/vector_arith.isa
index 12eab95246..c808f08ee4 100644
--- a/src/arch/riscv/isa/templates/vector_arith.isa
+++ b/src/arch/riscv/isa/templates/vector_arith.isa
@@ -951,6 +951,21 @@ Fault
 
 }};
 
+def template Vector1Vs1VdMaskDeclare {{
+
+template<typename ElemType>
+class %(class_name)s : public %(base_class)s {
+private:
+    RegId srcRegIdxArr[3];
+    RegId destRegIdxArr[1];
+    bool vm;
+public:
+    %(class_name)s(ExtMachInst _machInst);
+    Fault execute(ExecContext* xc, trace::InstRecord* traceData)const override;
+    using %(base_class)s::generateDisassembly;
+};
+
+}};
 
 def template Vector1Vs1VdMaskConstructor {{