diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index d69bea2f0e..4f69a3f4a7 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -2082,7 +2082,8 @@ del wrap
     # 'def [signed] bitfield <ID> [<first>:<last>]'
     # This generates a preprocessor macro in the output file.
     def p_def_bitfield_0(self, t):
-        'def_bitfield : DEF opt_signed BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI'
+        'def_bitfield : DEF opt_signed ' \
+                'BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI'
         expr = 'bits(machInst, %2d, %2d)' % (t[6], t[8])
         if (t[2] == 'signed'):
             expr = 'sext<%d>(%s)' % (t[6] - t[8] + 1, expr)