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Merge ktlim@zizzer:/bk/newmem

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into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge

src/base/traceflags.py:
src/cpu/SConscript:
    Hand merge.
src/cpu/o3/alpha/params.hh:
    Hand merge.  This needs to get changed.

--HG--
rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh
rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py
extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
This commit is contained in:
Kevin Lim
2006-07-05 16:08:18 -04:00
parent 4201ec84b2 ae78c46531
commit b973fae85d
10 changed files with 102 additions and 26 deletions
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8
src/python/m5/objects/O3CPU.py
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@@ -37,12 +37,10 @@ class DerivO3CPU(BaseCPU):
"Issue/Execute/Writeback delay")
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
"to the IEW stage)")
dispatchWidth = Param.Unsigned("Dispatch width")
issueWidth = Param.Unsigned("Issue width")
executeWidth = Param.Unsigned("Execute width")
executeIntWidth = Param.Unsigned("Integer execute width")
executeFloatWidth = Param.Unsigned("Floating point execute width")
executeBranchWidth = Param.Unsigned("Branch execute width")
executeMemoryWidth = Param.Unsigned("Memory execute width")
wbWidth = Param.Unsigned("Writeback width")
wbDepth = Param.Unsigned("Writeback depth")
fuPool = Param.FUPool(NULL, "Functional Unit pool")
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "