sim: Add a system-global option to bypass caches

Virtualized CPUs and the fastmem mode of the atomic CPU require direct
access to physical memory. We currently require caches to be disabled
when using them to prevent chaos. This is not ideal when switching
between hardware virutalized CPUs and other CPU models as it would
require a configuration change on each switch. This changeset
introduces a new version of the atomic memory mode,
'atomic_noncaching', where memory accesses are inserted into the
memory system as atomic accesses, but bypass caches.

To make memory mode tests cleaner, the following methods are added to
the System class:

 * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'.
 * isTimingMode() -- True if the memory mode is 'timing'.
 * bypassCaches() -- True if caches should be bypassed.

The old getMemoryMode() and setMemoryMode() methods should never be
used from the C++ world anymore.

src/cpu/inorder/cpu.cc

@@ -812,7 +812,7 @@ InOrderCPU::init()
 void
 InOrderCPU::verifyMemoryMode() const
 {
-    if (system->getMemoryMode() != Enums::timing) {
+    if (!system->isTimingMode()) {
         fatal("The in-order CPU requires the memory system to be in "
               "'timing' mode.\n");
     }

src/cpu/o3/cpu.cc

@@ -1316,7 +1316,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::verifyMemoryMode() const
 {
-    if (system->getMemoryMode() != Enums::timing) {
+    if (!system->isTimingMode()) {
         fatal("The O3 CPU requires the memory system to be in "
               "'timing' mode.\n");
     }

src/cpu/simple/atomic.cc

@@ -212,7 +212,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 void
 AtomicSimpleCPU::verifyMemoryMode() const
 {
-    if (system->getMemoryMode() != Enums::atomic) {
+    if (!system->isAtomicMode()) {
         fatal("The atomic CPU requires the memory system to be in "
               "'atomic' mode.\n");
     }

src/cpu/simple/timing.cc

@@ -191,7 +191,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 void
 TimingSimpleCPU::verifyMemoryMode() const
 {
-    if (system->getMemoryMode() != Enums::timing) {
+    if (!system->isTimingMode()) {
         fatal("The timing CPU requires the memory system to be in "
               "'timing' mode.\n");
     }

src/cpu/testers/traffic_gen/traffic_gen.cc

@@ -83,10 +83,8 @@ TrafficGen::init()
     if (!port.isConnected())
         fatal("The port of %s is not connected!\n", name());
 
-    Enums::MemoryMode mode = system->getMemoryMode();
-
     // if the system is in timing mode active the request generator
-    if (mode == Enums::timing) {
+    if (system->isTimingMode()) {
         DPRINTF(TrafficGen, "Timing mode, activating request generator\n");
 
         // enter initial state
@@ -101,7 +99,7 @@ void
 TrafficGen::initState()
 {
     // when not restoring from a checkpoint, make sure we kick things off
-    if (system->getMemoryMode() == Enums::timing) {
+    if (system->isTimingMode()) {
         Tick nextStateGraphEvent = stateGraph.nextEventTick();
         schedule(updateStateGraphEvent, nextStateGraphEvent);
     } else {