gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tony Gutierrez
committed by
Anthony Gutierrez
Anthony Gutierrez
parent
b0eac7857a
commit
b8da9abba7
@@ -31,161 +31,116 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __WAVEFRONT_HH__
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#define __WAVEFRONT_HH__
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#ifndef __GPU_COMPUTE_WAVEFRONT_HH__
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#define __GPU_COMPUTE_WAVEFRONT_HH__
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#include <cassert>
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#include <deque>
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#include <list>
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#include <memory>
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#include <stack>
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#include <unordered_map>
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#include <vector>
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#include "arch/gpu_isa.hh"
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#include "base/logging.hh"
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#include "base/types.hh"
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#include "config/the_gpu_isa.hh"
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#include "gpu-compute/condition_register_state.hh"
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#include "gpu-compute/compute_unit.hh"
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#include "gpu-compute/dispatcher.hh"
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "gpu-compute/hsa_queue_entry.hh"
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#include "gpu-compute/lds_state.hh"
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#include "gpu-compute/misc.hh"
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#include "gpu-compute/ndrange.hh"
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#include "params/Wavefront.hh"
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#include "sim/sim_object.hh"
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static const int MAX_NUM_INSTS_PER_WF = 12;
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/**
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* A reconvergence stack entry conveys the necessary state to implement
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* control flow divergence.
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*/
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struct ReconvergenceStackEntry {
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/**
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* PC of current instruction.
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*/
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uint32_t pc;
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/**
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* PC of the immediate post-dominator instruction, i.e., the value of
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* @a pc for the first instruction that will be executed by the wavefront
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* when a reconvergence point is reached.
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*/
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uint32_t rpc;
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/**
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* Execution mask.
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*/
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VectorMask execMask;
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};
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/*
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* Arguments for the hsail opcode call, are user defined and variable length.
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* The hardware/finalizer can support arguments in hardware or use memory to
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* pass arguments. For now, let's assume that an unlimited number of arguments
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* are supported in hardware (the compiler inlines functions whenver it can
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* anyways, so unless someone is interested in the implications of linking/
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* library functions, I think this is a reasonable assumption given the typical
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* size of an OpenCL kernel).
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*
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* Note that call args are different than kernel arguments:
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* * All work-items in a kernel refer the same set of kernel arguments
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* * Each work-item has it's on set of call args. So a call argument at
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* address 0x4 is different for work-item 0 and work-item 1.
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*
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* Ok, the table below shows an example of how we organize the call arguments in
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* the CallArgMem class.
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*
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* int foo(int arg1, double arg2)
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* ___________________________________________________
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* | 0: return.0 | 4: return.1 | ... | 252: return.63 |
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* |---------------------------------------------------|
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* | 256: arg1.0 | 260: arg1.1 | ... | 508: arg1.63 |
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* |---------------------------------------------------|
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* | 512: arg2.0 | 520: arg2.1 | ... | 1016: arg2.63 |
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* ___________________________________________________
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*/
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class CallArgMem
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{
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public:
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// pointer to buffer for storing function arguments
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uint8_t *mem;
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int wfSize;
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// size of function args
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int funcArgsSizePerItem;
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template<typename CType>
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int
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getLaneOffset(int lane, int addr)
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{
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return addr * wfSize + sizeof(CType) * lane;
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}
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CallArgMem(int func_args_size_per_item, int wf_size)
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: wfSize(wf_size), funcArgsSizePerItem(func_args_size_per_item)
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{
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mem = (uint8_t*)malloc(funcArgsSizePerItem * wfSize);
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}
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~CallArgMem()
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{
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free(mem);
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}
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template<typename CType>
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uint8_t*
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getLaneAddr(int lane, int addr)
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{
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return mem + getLaneOffset<CType>(lane, addr);
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}
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template<typename CType>
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void
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setLaneAddr(int lane, int addr, CType val)
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{
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*((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val;
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}
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};
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class Wavefront : public SimObject
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{
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public:
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enum itype_e {I_ALU,I_GLOBAL,I_SHARED,I_FLAT,I_PRIVATE};
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enum status_e {S_STOPPED,S_RETURNING,S_RUNNING};
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// Base pointer for array of instruction pointers
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uint64_t basePtr;
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enum status_e {
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// wavefront is stalled
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S_STOPPED,
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// wavefront is returning from a kernel
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S_RETURNING,
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// wavefront is running normally
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S_RUNNING,
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// wavefront is stalled
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S_STALLED,
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/**
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* wavefront has unsatisfied wait counts
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*
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* while in this state the WF will only execute if
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* the oldest instruction is the waitcnt. while in
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* S_WAITCNT, the wavefront will not be ready until
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* all of its waitcnts have been satisfied. the
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* scoreboard ready() function will check the status
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* of the waitcnts whenever the WF is in S_WAITCNT,
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* and once they are satisfied, it will resume normal
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* operation.
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*/
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S_WAITCNT
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};
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uint32_t oldBarrierCnt;
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uint32_t barrierCnt;
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uint32_t barrierId;
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uint32_t barrierSlots;
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status_e status;
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// HW slot id where the WF is mapped to inside a SIMD unit
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int wfSlotId;
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const int wfSlotId;
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int kernId;
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// SIMD unit where the WV has been scheduled
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int simdId;
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const int simdId;
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// id of the execution unit (or pipeline) where the oldest instruction
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// of the WF is scheduled
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int execUnitId;
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int flatLmUnitId;
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int flatGmUnitId;
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// pointer to parent CU
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ComputeUnit *computeUnit;
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int maxIbSize;
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std::deque<GPUDynInstPtr> instructionBuffer;
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bool pendingFetch;
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bool dropFetch;
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// last tick during which all WFs in the CU are not idle
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Tick lastNonIdleTick;
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// Condition Register State (for HSAIL simulations only)
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class ConditionRegisterState *condRegState;
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// number of single precision VGPRs required by WF
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uint32_t maxSpVgprs;
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// number of double precision VGPRs required by WF
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uint32_t maxDpVgprs;
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// map virtual to physical vector register
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uint32_t remap(uint32_t vgprIndex, uint32_t size, uint8_t mode=0);
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void resizeRegFiles(int num_cregs, int num_sregs, int num_dregs);
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// Execution unit resource ID's associated with this WF
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// These are static mappings set at WF slot construction and
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// based off of the simdId and wfSlotId.
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// Index to scalarALUs resource vector in CU
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int scalarAlu;
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// Indices into readyList/dispatchList of resources used by this
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// wavefront
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int scalarAluGlobalIdx;
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int globalMem;
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int localMem;
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int scalarMem;
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// number of VGPRs required by WF
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uint32_t maxVgprs;
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// number of SGPRs required by WF
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uint32_t maxSgprs;
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void freeResources();
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GPUDynInstPtr nextInstr();
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void setStatus(status_e newStatus);
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status_e getStatus() { return status; }
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void resizeRegFiles(int num_vregs, int num_sregs);
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bool isGmInstruction(GPUDynInstPtr ii);
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bool isLmInstruction(GPUDynInstPtr ii);
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bool isOldestInstWaitcnt();
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bool isOldestInstGMem();
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bool isOldestInstLMem();
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bool isOldestInstPrivMem();
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bool isOldestInstFlatMem();
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bool isOldestInstALU();
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bool isOldestInstVectorALU();
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bool isOldestInstScalarALU();
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bool isOldestInstScalarMem();
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bool isOldestInstBarrier();
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// used for passing spill address to DDInstGPU
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std::vector<Addr> lastAddr;
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std::vector<uint32_t> workItemId[3];
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@@ -199,36 +154,44 @@ class Wavefront : public SimObject
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/* the actual WG size can differ than the maximum size */
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uint32_t actualWgSz[3];
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uint32_t actualWgSzTotal;
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void computeActualWgSz(NDRange *ndr);
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void computeActualWgSz(HSAQueueEntry *task);
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// wavefront id within a workgroup
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uint32_t wfId;
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uint32_t maxDynWaveId;
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uint32_t dispatchId;
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// outstanding global+local memory requests
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uint32_t outstandingReqs;
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// memory requests between scoreboard
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// and execute stage not yet executed
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uint32_t memReqsInPipe;
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// vector and scalar memory requests pending in memory system
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int outstandingReqs;
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// outstanding global memory write requests
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uint32_t outstandingReqsWrGm;
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int outstandingReqsWrGm;
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// outstanding local memory write requests
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uint32_t outstandingReqsWrLm;
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int outstandingReqsWrLm;
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// outstanding global memory read requests
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uint32_t outstandingReqsRdGm;
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int outstandingReqsRdGm;
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// outstanding local memory read requests
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uint32_t outstandingReqsRdLm;
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uint32_t rdLmReqsInPipe;
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uint32_t rdGmReqsInPipe;
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uint32_t wrLmReqsInPipe;
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uint32_t wrGmReqsInPipe;
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int outstandingReqsRdLm;
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// outstanding scalar memory read requests
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int scalarOutstandingReqsRdGm;
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// outstanding scalar memory write requests
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int scalarOutstandingReqsWrGm;
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int rdLmReqsInPipe;
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int rdGmReqsInPipe;
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int wrLmReqsInPipe;
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int wrGmReqsInPipe;
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int scalarRdGmReqsInPipe;
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int scalarWrGmReqsInPipe;
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int memTraceBusy;
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uint64_t lastTrace;
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// number of vector registers reserved by WF
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// number of virtual vector registers reserved by WF
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int reservedVectorRegs;
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// number of virtual scalar registers reserved by WF
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int reservedScalarRegs;
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// Index into the Vector Register File's namespace where the WF's registers
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// will live while the WF is executed
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uint32_t startVgprIndex;
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// Index into the Scalar Register File's namespace where the WF's registers
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// will live while the WF is executed
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uint32_t startSgprIndex;
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// Old value of destination gpr (for trace)
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std::vector<uint32_t> oldVgpr;
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@@ -257,64 +220,63 @@ class Wavefront : public SimObject
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// to this workgroup (thus this wavefront)
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LdsChunk *ldsChunk;
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// A pointer to the spill area
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Addr spillBase;
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// The size of the spill area
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uint32_t spillSizePerItem;
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// The vector width of the spill area
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uint32_t spillWidth;
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// A pointer to the private memory area
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Addr privBase;
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// The size of the private memory area
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uint32_t privSizePerItem;
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// A pointer ot the read-only memory area
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Addr roBase;
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// size of the read-only memory area
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uint32_t roSize;
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// pointer to buffer for storing kernel arguments
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uint8_t *kernelArgs;
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// unique WF id over all WFs executed across all CUs
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uint64_t wfDynId;
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// number of times instruction issue for this wavefront is blocked
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// due to VRF port availability
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Stats::Scalar numTimesBlockedDueVrfPortAvail;
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// Wavefront slot stats
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// Number of instructions executed by this wavefront slot across all
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// dynamic wavefronts
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Stats::Scalar numInstrExecuted;
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// Number of cycles this WF spends in SCH stage
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Stats::Scalar schCycles;
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// Number of stall cycles encounterd by this WF in SCH stage
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Stats::Scalar schStalls;
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// The following stats sum to the value of schStalls, and record, per
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// WF slot, what the cause of each stall was at a coarse granularity.
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// Cycles WF is selected by scheduler, but RFs cannot support instruction
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Stats::Scalar schRfAccessStalls;
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// Cycles spent waiting for execution resources
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Stats::Scalar schResourceStalls;
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// cycles spent waiting for RF reads to complete in SCH stage
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Stats::Scalar schOpdNrdyStalls;
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// LDS arbitration stall cycles. WF attempts to execute LM instruction,
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// but another wave is executing FLAT, which requires LM and GM and forces
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// this WF to stall.
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Stats::Scalar schLdsArbStalls;
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// number of times an instruction of a WF is blocked from being issued
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// due to WAR and WAW dependencies
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Stats::Scalar numTimesBlockedDueWAXDependencies;
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// number of times an instruction of a WF is blocked from being issued
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// due to WAR and WAW dependencies
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Stats::Scalar numTimesBlockedDueRAWDependencies;
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// distribution of executed instructions based on their register
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// operands; this is used to highlight the load on the VRF
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Stats::Distribution srcRegOpDist;
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Stats::Distribution dstRegOpDist;
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// Functions to operate on call argument memory
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// argument memory for hsail call instruction
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CallArgMem *callArgMem;
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void
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initCallArgMem(int func_args_size_per_item, int wf_size)
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{
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callArgMem = new CallArgMem(func_args_size_per_item, wf_size);
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}
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// dyn inst id (per SIMD) of last instruction exec from this wave
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uint64_t lastInstExec;
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template<typename CType>
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CType
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readCallArgMem(int lane, int addr)
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{
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return *((CType*)(callArgMem->getLaneAddr<CType>(lane, addr)));
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}
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// Distribution to track the distance between producer and consumer
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// for vector register values
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Stats::Distribution vecRawDistance;
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// Map to track the dyn instruction id of each vector register value
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// produced, indexed by physical vector register ID
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std::unordered_map<int,uint64_t> rawDist;
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template<typename CType>
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void
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writeCallArgMem(int lane, int addr, CType val)
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{
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callArgMem->setLaneAddr<CType>(lane, addr, val);
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}
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// Distribution to track the number of times every vector register
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// value produced is consumed.
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Stats::Distribution readsPerWrite;
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// Counts the number of reads performed to each physical register
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// - counts are reset to 0 for each dynamic wavefront launched
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std::vector<int> vecReads;
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void initRegState(HSAQueueEntry *task, int wgSizeInWorkItems);
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// context for save/restore
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uint8_t *context;
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typedef WavefrontParams Params;
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Wavefront(const Params *p);
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@@ -327,50 +289,31 @@ class Wavefront : public SimObject
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computeUnit = cu;
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}
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void validateRequestCounters();
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void start(uint64_t _wfDynId, uint64_t _base_ptr);
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void exec();
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void updateResources();
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int ready(itype_e type);
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bool instructionBufferHasBranch();
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// called by SCH stage to reserve
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std::vector<int> reserveResources();
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bool stopFetch();
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void regStats();
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VectorMask getPred() { return execMask() & initMask; }
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bool waitingAtBarrier(int lane);
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void pushToReconvergenceStack(uint32_t pc, uint32_t rpc,
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const VectorMask& exec_mask);
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void popFromReconvergenceStack();
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uint32_t pc() const;
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uint32_t rpc() const;
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VectorMask execMask() const;
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Addr pc() const;
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void pc(Addr new_pc);
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VectorMask& execMask();
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bool execMask(int lane) const;
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void pc(uint32_t new_pc);
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void discardFetch();
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/**
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* Returns the size of the static hardware context of a particular wavefront
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* This should be updated everytime the context is changed
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*/
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uint32_t getStaticContextSize() const;
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bool waitCntsSatisfied();
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void setWaitCnts(int vm_wait_cnt, int exp_wait_cnt, int lgkm_wait_cnt);
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void clearWaitCnts();
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/**
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* Returns the hardware context as a stream of bytes
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* This method is designed for HSAIL execution
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*/
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void getContext(const void *out);
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/**
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* Sets the hardware context fromt a stream of bytes
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* This method is designed for HSAIL execution
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*/
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void setContext(const void *in);
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/** Freeing VRF space */
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void freeRegisterFile();
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TheGpuISA::GPUISA&
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gpuISA()
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@@ -380,14 +323,32 @@ class Wavefront : public SimObject
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private:
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TheGpuISA::GPUISA _gpuISA;
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void reserveGmResource(GPUDynInstPtr ii);
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void reserveLmResource(GPUDynInstPtr ii);
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/**
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* Stack containing Control Flow Graph nodes (i.e., kernel instructions)
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* to be visited by the wavefront, and the associated execution masks. The
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* reconvergence stack grows every time the wavefront reaches a divergence
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* point (branch instruction), and shrinks every time the wavefront
|
||||
* reaches a reconvergence point (immediate post-dominator instruction).
|
||||
* the following are used for waitcnt instructions
|
||||
* vmWaitCnt: once set, we wait for the oustanding
|
||||
* number of vector mem instructions to be
|
||||
* at, or below vmWaitCnt.
|
||||
*
|
||||
* expWaitCnt: once set, we wait for the outstanding
|
||||
* number outstanding VM writes or EXP
|
||||
* insts to be at, or below expWaitCnt.
|
||||
*
|
||||
* lgkmWaitCnt: once set, we wait for the oustanding
|
||||
* number of LDS, GDS, scalar memory,
|
||||
* and message instructions to be at, or
|
||||
* below lgkmCount. we currently do not
|
||||
* support GDS/message ops.
|
||||
*/
|
||||
std::deque<std::unique_ptr<ReconvergenceStackEntry>> reconvergenceStack;
|
||||
int vmWaitCnt;
|
||||
int expWaitCnt;
|
||||
int lgkmWaitCnt;
|
||||
status_e status;
|
||||
Addr _pc;
|
||||
VectorMask _execMask;
|
||||
};
|
||||
|
||||
#endif // __WAVEFRONT_HH__
|
||||
#endif // __GPU_COMPUTE_WAVEFRONT_HH__
|
||||
|
||||
Reference in New Issue
Block a user