gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
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Tony Gutierrez
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Anthony Gutierrez
Anthony Gutierrez
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src/gpu-compute/kernel_code.hh
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src/gpu-compute/kernel_code.hh
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/*
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* Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Anthony Gutierrez
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*/
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#ifndef __GPU_COMPUTE_KERNEL_CODE_HH__
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#define __GPU_COMPUTE_KERNEL_CODE_HH__
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#include <bitset>
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#include <cstdint>
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/**
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* these enums represent the indices into the
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* initialRegState bitfields in HsaKernelInfo.
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* each bit specifies whether or not the
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* particular piece of state that the bit
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* corresponds to should be initialized into
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* the VGPRs/SGPRs. the order in which the
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* fields are placed matters, as all enabled
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* pieces of state will be initialized into
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* contiguous registers in the same order
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* as their position in the bitfield - which
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* is specified in the HSA ABI.
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*/
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enum ScalarRegInitFields : int
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{
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PrivateSegBuf = 0,
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DispatchPtr = 1,
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QueuePtr = 2,
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KernargSegPtr = 3,
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DispatchId = 4,
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FlatScratchInit = 5,
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PrivateSegSize = 6,
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GridWorkgroupCountX = 7,
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GridWorkgroupCountY = 8,
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GridWorkgroupCountZ = 9,
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WorkgroupIdX = 10,
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WorkgroupIdY = 11,
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WorkgroupIdZ = 12,
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WorkgroupInfo = 13,
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PrivSegWaveByteOffset = 14,
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NumScalarInitFields = 15
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};
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enum VectorRegInitFields : int
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{
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WorkitemIdX = 0,
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WorkitemIdY = 1,
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WorkitemIdZ = 2,
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NumVectorInitFields = 3
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};
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struct AMDKernelCode
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{
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uint32_t amd_kernel_code_version_major;
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uint32_t amd_kernel_code_version_minor;
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uint16_t amd_machine_kind;
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uint16_t amd_machine_version_major;
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uint16_t amd_machine_version_minor;
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uint16_t amd_machine_version_stepping;
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int64_t kernel_code_entry_byte_offset;
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int64_t kernel_code_prefetch_byte_offset;
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uint64_t kernel_code_prefetch_byte_size;
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uint64_t max_scratch_backing_memory_byte_size;
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/**
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* The fields below are used to set program settings for
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* compute shaders. Here they are primarily used to setup
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* initial register state. See the following for full details
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* about kernel launch, state initialization, and the AMD kernel
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* code object: https://github.com/RadeonOpenCompute/ROCm_Documentation/
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* blob/master/ROCm_Compiler_SDK/ROCm-Codeobj-format.rst
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* #initial-kernel-register-state
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*/
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// the 32b below here represent the fields of
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// the COMPUTE_PGM_RSRC1 register
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uint32_t granulated_workitem_vgpr_count : 6;
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uint32_t granulated_wavefront_sgpr_count : 4;
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uint32_t priority : 2;
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uint32_t float_mode_round_32 : 2;
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uint32_t float_mode_round_16_64 : 2;
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uint32_t float_mode_denorm_32 : 2;
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uint32_t float_mode_denorm_16_64 : 2;
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uint32_t priv : 1;
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uint32_t enable_dx10_clamp : 1;
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uint32_t debug_mode : 1;
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uint32_t enable_ieee_mode : 1;
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uint32_t bulky : 1;
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uint32_t cdbg_user : 1;
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uint32_t compute_pgm_rsrc1_reserved : 6;
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// end COMPUTE_PGM_RSRC1 register
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// the 32b below here represent the fields of
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// the COMPUTE_PGM_RSRC2 register
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uint32_t enable_sgpr_private_segment_wave_byte_offset : 1;
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uint32_t user_sgpr_count : 5;
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uint32_t enable_trap_handler : 1;
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uint32_t enable_sgpr_workgroup_id_x : 1;
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uint32_t enable_sgpr_workgroup_id_y : 1;
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uint32_t enable_sgpr_workgroup_id_z : 1;
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uint32_t enable_sgpr_workgroup_info : 1;
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uint32_t enable_vgpr_workitem_id_y : 1;
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uint32_t enable_vgpr_workitem_id_z : 1;
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uint32_t enable_exception_address_watch : 1;
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uint32_t enable_exception_memory_violation : 1;
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uint32_t granulated_lds_size : 9;
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uint32_t enable_exception_ieee_754_fp_invalid_operation : 1;
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uint32_t enable_exception_fp_denormal_source : 1;
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uint32_t enable_exception_ieee_754_fp_division_by_zero : 1;
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uint32_t enable_exception_ieee_754_fp_overflow : 1;
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uint32_t enable_exception_ieee_754_fp_underflow : 1;
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uint32_t enable_exception_ieee_754_fp_inexact : 1;
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uint32_t enable_exception_int_divide_by_zero : 1;
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uint32_t compute_pgm_rsrc2_reserved : 1;
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// end COMPUTE_PGM_RSRC2
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// the 32b below here represent the fields of
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// KERNEL_CODE_PROPERTIES
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uint32_t enable_sgpr_private_segment_buffer : 1;
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uint32_t enable_sgpr_dispatch_ptr : 1;
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uint32_t enable_sgpr_queue_ptr : 1;
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uint32_t enable_sgpr_kernarg_segment_ptr : 1;
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uint32_t enable_sgpr_dispatch_id : 1;
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uint32_t enable_sgpr_flat_scratch_init : 1;
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uint32_t enable_sgpr_private_segment_size : 1;
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uint32_t enable_sgpr_grid_workgroup_count_x : 1;
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uint32_t enable_sgpr_grid_workgroup_count_y : 1;
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uint32_t enable_sgpr_grid_workgroup_count_z : 1;
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uint32_t kernel_code_properties_reserved1 : 6;
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uint32_t enable_ordered_append_gds : 1;
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uint32_t private_element_size : 2;
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uint32_t is_ptr64 : 1;
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uint32_t is_dynamic_callstack : 1;
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uint32_t is_debug_enabled : 1;
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uint32_t is_xnack_enabled : 1;
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uint32_t kernel_code_properties_reserved2 : 9;
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// end KERNEL_CODE_PROPERTIES
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uint32_t workitem_private_segment_byte_size;
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uint32_t workgroup_group_segment_byte_size;
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uint32_t gds_segment_byte_size;
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uint64_t kernarg_segment_byte_size;
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uint32_t workgroup_fbarrier_count;
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uint16_t wavefront_sgpr_count;
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uint16_t workitem_vgpr_count;
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uint16_t reserved_vgpr_first;
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uint16_t reserved_vgpr_count;
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uint16_t reserved_sgpr_first;
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uint16_t reserved_sgpr_count;
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uint16_t debug_wavefront_private_segment_offset_sgpr;
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uint16_t debug_private_segment_buffer_sgpr;
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uint8_t kernarg_segment_alignment;
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uint8_t group_segment_alignment;
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uint8_t private_segment_alignment;
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uint8_t wavefront_size;
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int32_t call_convention;
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uint8_t reserved[12];
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uint64_t runtime_loader_kernel_symbol;
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uint64_t control_directives[16];
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};
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#endif // __GPU_COMPUTE_KERNEL_CODE_HH__
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