gpu-compute, mem-ruby, configs: Add GCN3 ISA support to GPU model
Change-Id: Ibe46970f3ba25d62ca2ade5cbc2054ad746b2254 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29912 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
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Tony Gutierrez
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Anthony Gutierrez
Anthony Gutierrez
parent
b0eac7857a
commit
b8da9abba7
@@ -59,6 +59,7 @@ class GPUStaticInst : public GPUStaticInstFlags
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{
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public:
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GPUStaticInst(const std::string &opcode);
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virtual ~GPUStaticInst() { }
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void instAddr(int inst_addr) { _instAddr = inst_addr; }
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int instAddr() const { return _instAddr; }
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int nextInstAddr() const { return _instAddr + instSize(); }
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@@ -71,15 +72,18 @@ class GPUStaticInst : public GPUStaticInstFlags
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int ipdInstNum() const { return _ipdInstNum; }
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virtual TheGpuISA::ScalarRegU32 srcLiteral() const { return 0; }
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virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
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virtual void generateDisassembly() = 0;
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const std::string& disassemble();
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virtual int getNumOperands() = 0;
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virtual bool isCondRegister(int operandIndex) = 0;
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virtual bool isScalarRegister(int operandIndex) = 0;
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virtual bool isVectorRegister(int operandIndex) = 0;
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virtual bool isSrcOperand(int operandIndex) = 0;
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virtual bool isDstOperand(int operandIndex) = 0;
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virtual bool isFlatScratchRegister(int opIdx) = 0;
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virtual bool isExecMaskRegister(int opIdx) = 0;
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virtual int getOperandSize(int operandIndex) = 0;
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virtual int getRegisterIndex(int operandIndex,
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@@ -88,12 +92,24 @@ class GPUStaticInst : public GPUStaticInstFlags
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virtual int numDstRegOperands() = 0;
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virtual int numSrcRegOperands() = 0;
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virtual bool isValid() const = 0;
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virtual int coalescerTokenCount() const { return 0; }
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int numDstVecOperands();
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int numSrcVecOperands();
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int numDstVecDWORDs();
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int numSrcVecDWORDs();
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int numOpdDWORDs(int operandIdx);
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bool isALU() const { return _flags[ALU]; }
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bool isBranch() const { return _flags[Branch]; }
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bool isCondBranch() const { return _flags[CondBranch]; }
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bool isNop() const { return _flags[Nop]; }
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bool isReturn() const { return _flags[Return]; }
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bool isEndOfKernel() const { return _flags[EndOfKernel]; }
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bool isKernelLaunch() const { return _flags[KernelLaunch]; }
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bool isSDWAInst() const { return _flags[IsSDWA]; }
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bool isDPPInst() const { return _flags[IsDPP]; }
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bool
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isUnconditionalJump() const
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@@ -105,7 +121,7 @@ class GPUStaticInst : public GPUStaticInstFlags
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bool isWaitcnt() const { return _flags[Waitcnt]; }
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bool isBarrier() const { return _flags[MemBarrier]; }
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bool isMemFence() const { return _flags[MemFence]; }
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bool isMemSync() const { return _flags[MemSync]; }
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bool isMemRef() const { return _flags[MemoryRef]; }
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bool isFlat() const { return _flags[Flat]; }
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bool isLoad() const { return _flags[Load]; }
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@@ -125,6 +141,13 @@ class GPUStaticInst : public GPUStaticInstFlags
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bool writesSCC() const { return _flags[WritesSCC]; }
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bool readsVCC() const { return _flags[ReadsVCC]; }
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bool writesVCC() const { return _flags[WritesVCC]; }
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// Identify instructions that implicitly read the Execute mask
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// as a source operand but not to dictate which threads execute.
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bool readsEXEC() const { return _flags[ReadsEXEC]; }
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bool writesEXEC() const { return _flags[WritesEXEC]; }
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bool readsMode() const { return _flags[ReadsMode]; }
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bool writesMode() const { return _flags[WritesMode]; }
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bool ignoreExec() const { return _flags[IgnoreExec]; }
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bool isAtomicAnd() const { return _flags[AtomicAnd]; }
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bool isAtomicOr() const { return _flags[AtomicOr]; }
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@@ -166,34 +189,29 @@ class GPUStaticInst : public GPUStaticInstFlags
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bool isReadOnlySeg() const { return _flags[ReadOnlySegment]; }
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bool isSpillSeg() const { return _flags[SpillSegment]; }
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bool isWorkitemScope() const { return _flags[WorkitemScope]; }
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bool isWavefrontScope() const { return _flags[WavefrontScope]; }
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bool isWorkgroupScope() const { return _flags[WorkgroupScope]; }
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bool isDeviceScope() const { return _flags[DeviceScope]; }
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bool isSystemScope() const { return _flags[SystemScope]; }
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bool isNoScope() const { return _flags[NoScope]; }
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bool isRelaxedOrder() const { return _flags[RelaxedOrder]; }
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bool isAcquire() const { return _flags[Acquire]; }
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bool isRelease() const { return _flags[Release]; }
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bool isAcquireRelease() const { return _flags[AcquireRelease]; }
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bool isNoOrder() const { return _flags[NoOrder]; }
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/**
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* Coherence domain of a memory instruction. Only valid for
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* machine ISA. The coherence domain specifies where it is
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* possible to perform memory synchronization, e.g., acquire
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* or release, from the shader kernel.
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* Coherence domain of a memory instruction. The coherence domain
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* specifies where it is possible to perform memory synchronization
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* (e.g., acquire or release) from the shader kernel.
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*
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* isGloballyCoherent(): returns true if kernel is sharing memory
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* with other work-items on the same device (GPU)
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* isGloballyCoherent(): returns true if WIs share same device
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* isSystemCoherent(): returns true if WIs or threads in different
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* devices share memory
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*
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* isSystemCoherent(): returns true if kernel is sharing memory
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* with other work-items on a different device (GPU) or the host (CPU)
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*/
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bool isGloballyCoherent() const { return _flags[GloballyCoherent]; }
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bool isSystemCoherent() const { return _flags[SystemCoherent]; }
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// Floating-point instructions
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bool isF16() const { return _flags[F16]; }
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bool isF32() const { return _flags[F32]; }
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bool isF64() const { return _flags[F64]; }
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// FMA, MAC, MAD instructions
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bool isFMA() const { return _flags[FMA]; }
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bool isMAC() const { return _flags[MAC]; }
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bool isMAD() const { return _flags[MAD]; }
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virtual int instSize() const = 0;
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// only used for memory instructions
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@@ -217,37 +235,36 @@ class GPUStaticInst : public GPUStaticInstFlags
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// For flat memory accesses
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Enums::StorageClassType executed_as;
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void setFlag(Flags flag) { _flags[flag] = true; }
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void setFlag(Flags flag) {
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_flags[flag] = true;
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virtual void
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execLdAcq(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execLdAcq() on a non-load instruction.\n");
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}
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virtual void
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execSt(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execLdAcq() on a non-load instruction.\n");
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}
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virtual void
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execAtomic(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execAtomic() on a non-atomic instruction.\n");
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}
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virtual void
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execAtomicAcq(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execAtomicAcq() on a non-atomic instruction.\n");
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if (isGroupSeg()) {
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executed_as = Enums::SC_GROUP;
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} else if (isGlobalSeg()) {
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executed_as = Enums::SC_GLOBAL;
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} else if (isPrivateSeg()) {
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executed_as = Enums::SC_PRIVATE;
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} else if (isSpillSeg()) {
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executed_as = Enums::SC_SPILL;
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} else if (isReadOnlySeg()) {
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executed_as = Enums::SC_READONLY;
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} else if (isKernArgSeg()) {
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executed_as = Enums::SC_KERNARG;
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} else if (isArgSeg()) {
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executed_as = Enums::SC_ARG;
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}
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}
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const std::string& opcode() const { return _opcode; }
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protected:
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const std::string opcode;
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const std::string _opcode;
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std::string disassembly;
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int _instNum;
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int _instAddr;
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int srcVecOperands;
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int dstVecOperands;
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int srcVecDWORDs;
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int dstVecDWORDs;
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/**
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* Identifier of the immediate post-dominator instruction.
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*/
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@@ -262,9 +279,9 @@ class KernelLaunchStaticInst : public GPUStaticInst
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KernelLaunchStaticInst() : GPUStaticInst("kernel_launch")
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{
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setFlag(Nop);
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setFlag(KernelLaunch);
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setFlag(MemSync);
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setFlag(Scalar);
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setFlag(Acquire);
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setFlag(SystemScope);
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setFlag(GlobalSegment);
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}
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@@ -277,11 +294,14 @@ class KernelLaunchStaticInst : public GPUStaticInst
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void
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generateDisassembly() override
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{
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disassembly = opcode;
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disassembly = _opcode;
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}
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int getNumOperands() override { return 0; }
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bool isCondRegister(int operandIndex) override { return false; }
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bool isFlatScratchRegister(int opIdx) override { return false; }
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// return true if the Execute mask is explicitly used as a source
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// register operand
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bool isExecMaskRegister(int opIdx) override { return false; }
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bool isScalarRegister(int operandIndex) override { return false; }
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bool isVectorRegister(int operandIndex) override { return false; }
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bool isSrcOperand(int operandIndex) override { return false; }
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@@ -296,7 +316,6 @@ class KernelLaunchStaticInst : public GPUStaticInst
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int numDstRegOperands() override { return 0; }
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int numSrcRegOperands() override { return 0; }
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bool isValid() const override { return true; }
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int instSize() const override { return 0; }
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};
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