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misc: Update attribute syntax, and reorganize compiler.hh.

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This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 18:26:02 -07:00
parent 3c31a214b6
commit b877efa6d4
78 changed files with 242 additions and 208 deletions
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4
src/mem/cache/base.cc vendored
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@@ -855,7 +855,7 @@ BaseCache::updateCompressionData(CacheBlk *blk, const uint64_t* data,
// the bigger block
// Get previous compressed size
const std::size_t M5_VAR_USED prev_size = compression_blk->getSizeBits();
M5_VAR_USED const std::size_t prev_size = compression_blk->getSizeBits();
// Check if new data is co-allocatable
const bool is_co_allocatable = superblock->isCompressed(compression_blk) &&
@@ -2320,7 +2320,7 @@ BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
if (cache->system->bypassCaches()) {
// Just forward the packet if caches are disabled.
// @todo This should really enqueue the packet rather
bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt);
M5_VAR_USED bool success = cache->memSidePort.sendTimingReq(pkt);
assert(success);
return true;
} else if (tryTiming(pkt)) {

6
src/mem/cache/cache.cc vendored
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@@ -447,7 +447,7 @@ Cache::recvTimingReq(PacketPtr pkt)
// this express snoop travels towards the memory, and at
// every crossbar it is snooped upwards thus reaching
// every cache in the system
bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt);
M5_VAR_USED bool success = memSidePort.sendTimingReq(snoop_pkt);
// express snoops always succeed
assert(success);
@@ -992,7 +992,7 @@ Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
// responds in atomic mode, so remember a few things about the
// original packet up front
bool invalidate = pkt->isInvalidate();
bool M5_VAR_USED needs_writable = pkt->needsWritable();
M5_VAR_USED bool needs_writable = pkt->needsWritable();
// at the moment we could get an uncacheable write which does not
// have the invalidate flag, and we need a suitable way of dealing
@@ -1391,7 +1391,7 @@ Cache::sendMSHRQueuePacket(MSHR* mshr)
// prefetchSquash first may result in the MSHR being
// prematurely deallocated.
if (snoop_pkt.cacheResponding()) {
auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
M5_VAR_USED auto r = outstandingSnoop.insert(snoop_pkt.req);
assert(r.second);
// if we are getting a snoop response with no sharers it

2
src/mem/cache/tags/fa_lru.cc vendored
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@@ -117,7 +117,7 @@ void
FALRU::invalidate(CacheBlk *blk)
{
// Erase block entry reference in the hash table
auto num_erased M5_VAR_USED =
M5_VAR_USED auto num_erased =
tagHash.erase(std::make_pair(blk->tag, blk->isSecure()));
// Sanity check; only one block reference should be erased