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misc: Update attribute syntax, and reorganize compiler.hh.

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This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 18:26:02 -07:00
parent 3c31a214b6
commit b877efa6d4
78 changed files with 242 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/dev/arm/gic_v2.cc
View File

@@ -389,7 +389,7 @@ GicV2::writeDistributor(PacketPtr pkt)
const ContextID ctx = pkt->req->contextId();
const size_t data_sz = pkt->getSize();
uint32_t pkt_data M5_VAR_USED;
M5_VAR_USED uint32_t pkt_data;
switch (data_sz)
{
case 1:

2
src/dev/arm/smmu_v3_transl.hh
View File

@@ -97,7 +97,7 @@ class SMMUTranslationProcess : public SMMUProcess
TranslContext context;
Tick recvTick;
Tick M5_CLASS_VAR_USED faultTick;
M5_CLASS_VAR_USED Tick faultTick;
virtual void main(Yield &yield);

6
src/dev/hsa/hsa_packet_processor.cc
View File

@@ -126,7 +126,7 @@ HSAPacketProcessor::write(Packet *pkt)
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
// TODO: How to get pid??
Addr M5_VAR_USED daddr = pkt->getAddr() - pioAddr;
M5_VAR_USED Addr daddr = pkt->getAddr() - pioAddr;
DPRINTF(HSAPacketProcessor,
"%s: write of size %d to reg-offset %d (0x%x)\n",
@@ -256,7 +256,7 @@ void
HSAPacketProcessor::CmdQueueCmdDmaEvent::process()
{
uint32_t rl_idx = series_ctx->rl_idx;
AQLRingBuffer *aqlRingBuffer M5_VAR_USED =
M5_VAR_USED AQLRingBuffer *aqlRingBuffer =
hsaPP->regdQList[rl_idx]->qCntxt.aqlBuf;
HSAQueueDescriptor* qDesc =
hsaPP->regdQList[rl_idx]->qCntxt.qDesc;
@@ -590,7 +590,7 @@ HSAPacketProcessor::getCommandsFromHost(int pid, uint32_t rl_idx)
void
HSAPacketProcessor::displayQueueDescriptor(int pid, uint32_t rl_idx)
{
HSAQueueDescriptor* M5_VAR_USED qDesc = regdQList[rl_idx]->qCntxt.qDesc;
M5_VAR_USED HSAQueueDescriptor* qDesc = regdQList[rl_idx]->qCntxt.qDesc;
DPRINTF(HSAPacketProcessor,
"%s: pid[%d], basePointer[0x%lx], dBPointer[0x%lx], "
"writeIndex[0x%x], readIndex[0x%x], size(bytes)[0x%x]\n",

2
src/dev/hsa/hw_scheduler.cc
View File

@@ -118,7 +118,7 @@ HWScheduler::registerNewQueue(uint64_t hostReadIndexPointer,
// Check if this newly created queue can be directly mapped
// to registered queue list
bool M5_VAR_USED register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc);
M5_VAR_USED bool register_q = mapQIfSlotAvlbl(queue_id, aql_buf, q_desc);
schedWakeup();
DPRINTF(HSAPacketProcessor,
"%s: offset = %p, qID = %d, is_regd = %s, AL size %d\n",

2
src/dev/net/sinic.cc
View File

@@ -233,7 +233,7 @@ Device::read(PacketPtr pkt)
prepareRead(cpu, index);
uint64_t value M5_VAR_USED = 0;
M5_VAR_USED uint64_t value = 0;
if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
pkt->setLE(reg);

2
src/dev/net/tcp_iface.cc
View File

@@ -253,7 +253,7 @@ TCPIface::connect()
TCPIface::~TCPIface()
{
int M5_VAR_USED ret;
M5_VAR_USED int ret;
ret = close(sock);
assert(ret == 0);

8
src/dev/pci/copy_engine.cc
View File

@@ -305,19 +305,19 @@ CopyEngine::write(PacketPtr pkt)
///
if (size == sizeof(uint64_t)) {
uint64_t val M5_VAR_USED = pkt->getLE<uint64_t>();
M5_VAR_USED uint64_t val = pkt->getLE<uint64_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint32_t)) {
uint32_t val M5_VAR_USED = pkt->getLE<uint32_t>();
M5_VAR_USED uint32_t val = pkt->getLE<uint32_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint16_t)) {
uint16_t val M5_VAR_USED = pkt->getLE<uint16_t>();
M5_VAR_USED uint16_t val = pkt->getLE<uint16_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else if (size == sizeof(uint8_t)) {
uint8_t val M5_VAR_USED = pkt->getLE<uint8_t>();
M5_VAR_USED uint8_t val = pkt->getLE<uint8_t>();
DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
daddr, val);
} else {

4
src/dev/virtio/base.hh
View File

@@ -451,10 +451,10 @@ public:
typedef uint16_t Flags;
typedef uint16_t Index;
struct Header {
struct M5_ATTR_PACKED Header {
Flags flags;
Index index;
} M5_ATTR_PACKED;
};
VirtRing<T>(PortProxy &proxy, ByteOrder bo, uint16_t size) :
header{0, 0}, ring(size), _proxy(proxy), _base(0), byteOrder(bo)

8
src/dev/virtio/block.hh
View File

@@ -81,9 +81,9 @@ class VirtIOBlock : public VirtIODeviceBase
* @note This needs to be changed if the supported feature set
* changes!
*/
struct Config {
struct M5_ATTR_PACKED Config {
uint64_t capacity;
} M5_ATTR_PACKED;
};
Config config;
/** @{
@@ -122,11 +122,11 @@ class VirtIOBlock : public VirtIODeviceBase
/** @} */
/** VirtIO block device request as sent by guest */
struct BlkRequest {
struct M5_ATTR_PACKED BlkRequest {
RequestType type;
uint32_t reserved;
uint64_t sector;
} M5_ATTR_PACKED;
};
/**
* Device read request.

4
src/dev/virtio/console.hh
View File

@@ -77,10 +77,10 @@ class VirtIOConsole : public VirtIODeviceBase
* @note This needs to be changed if the multiport feature is
* announced!
*/
struct Config {
struct M5_ATTR_PACKED Config {
uint16_t cols;
uint16_t rows;
} M5_ATTR_PACKED;
};
/** Currently active configuration (host byte order) */
Config config;

8
src/dev/virtio/fs9p.hh
View File

@@ -50,14 +50,14 @@ struct VirtIO9PBaseParams;
typedef uint8_t P9MsgType;
typedef uint16_t P9Tag;
struct P9MsgHeader {
struct M5_ATTR_PACKED P9MsgHeader {
/** Length including header */
uint32_t len;
/** Message type */
P9MsgType type;
/** Message tag */
P9Tag tag;
} M5_ATTR_PACKED;
};
/** Convert p9 byte order (LE) to host byte order */
template <typename T> inline T
@@ -120,10 +120,10 @@ class VirtIO9PBase : public VirtIODeviceBase
* @note The fields in this structure depend on the features
* exposed to the guest.
*/
struct Config {
struct M5_ATTR_PACKED Config {
uint16_t len;
char tag[];
} M5_ATTR_PACKED;
};
/** Currently active configuration (host byte order) */
std::unique_ptr<Config> config;

4
src/dev/virtio/pci.cc
View File

@@ -65,7 +65,7 @@ PciVirtIO::~PciVirtIO()
Tick
PciVirtIO::read(PacketPtr pkt)
{
const unsigned M5_VAR_USED size(pkt->getSize());
M5_VAR_USED const unsigned size(pkt->getSize());
int bar;
Addr offset;
if (!getBAR(pkt->getAddr(), bar, offset))
@@ -146,7 +146,7 @@ PciVirtIO::read(PacketPtr pkt)
Tick
PciVirtIO::write(PacketPtr pkt)
{
const unsigned M5_VAR_USED size(pkt->getSize());
M5_VAR_USED const unsigned size(pkt->getSize());
int bar;
Addr offset;
if (!getBAR(pkt->getAddr(), bar, offset))