derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

misc: Update attribute syntax, and reorganize compiler.hh.

Browse Source 
This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 18:26:02 -07:00
parent 3c31a214b6
commit b877efa6d4
78 changed files with 242 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/o3/commit_impl.hh
View File

@@ -701,7 +701,7 @@ DefaultCommit<Impl>::tick()
// will be active.
_nextStatus = Active;
const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
M5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid);
DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
" ROB and ready to commit\n",

2
src/cpu/o3/lsq_impl.hh
View File

@@ -682,7 +682,7 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
// This comming request can be either load, store or atomic.
// Atomic request has a corresponding pointer to its atomic memory
// operation
bool isAtomic M5_VAR_USED = !isLoad && amo_op;
M5_VAR_USED bool isAtomic = !isLoad && amo_op;
ThreadID tid = cpu->contextToThread(inst->contextId());
auto cacheLineSize = cpu->cacheLineSize();

2
src/cpu/o3/mem_dep_unit_impl.hh
View File

@@ -270,7 +270,7 @@ MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list\n");
for (auto M5_VAR_USED producing_store : producing_stores)
for (M5_VAR_USED auto producing_store : producing_stores)
DPRINTF(MemDepUnit, "\tinst PC %s is dependent on [sn:%lli].\n",
inst->pcState(), producing_store);

2
src/cpu/o3/scoreboard.hh
View File

@@ -57,7 +57,7 @@ class Scoreboard
std::vector<bool> regScoreBoard;
/** The number of actual physical registers */
unsigned M5_CLASS_VAR_USED numPhysRegs;
M5_CLASS_VAR_USED unsigned numPhysRegs;
public:
/** Constructs a scoreboard.