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misc: Update attribute syntax, and reorganize compiler.hh.

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This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 18:26:02 -07:00
parent 3c31a214b6
commit b877efa6d4
78 changed files with 242 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/kvm/x86_cpu.cc
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@@ -68,7 +68,7 @@ using namespace X86ISA;
// data) is used to indicate that a segment has been accessed.
#define SEG_TYPE_BIT_ACCESSED 1
struct FXSave
struct M5_ATTR_PACKED FXSave
{
uint16_t fcw;
uint16_t fsw;
@@ -97,7 +97,7 @@ struct FXSave
uint8_t xmm[16][16];
uint64_t reserved[12];
} M5_ATTR_PACKED;
};
static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave");

2
src/cpu/minor/fetch1.cc
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@@ -388,7 +388,7 @@ void
Fetch1::minorTraceResponseLine(const std::string &name,
Fetch1::FetchRequestPtr response) const
{
const RequestPtr &request M5_VAR_USED = response->request;
M5_VAR_USED const RequestPtr &request = response->request;
if (response->packet && response->packet->isError()) {
MINORLINE(this, "id=F;%s vaddr=0x%x fault=\"error packet\"\n",

6
src/cpu/minor/lsq.cc
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@@ -77,7 +77,7 @@ LSQ::LSQRequest::tryToSuppressFault()
SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
TheISA::PCState old_pc = thread.pcState();
ExecContext context(port.cpu, thread, port.execute, inst);
Fault M5_VAR_USED fault = inst->translationFault;
M5_VAR_USED Fault fault = inst->translationFault;
// Give the instruction a chance to suppress a translation fault
inst->translationFault = inst->staticInst->initiateAcc(&context, nullptr);
@@ -334,7 +334,7 @@ LSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
{
port.numAccessesInDTLB--;
unsigned int M5_VAR_USED expected_fragment_index =
M5_VAR_USED unsigned int expected_fragment_index =
numTranslatedFragments;
numInTranslationFragments--;
@@ -475,7 +475,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
for (unsigned int fragment_index = 0; fragment_index < numFragments;
fragment_index++)
{
bool M5_VAR_USED is_last_fragment = false;
M5_VAR_USED bool is_last_fragment = false;
if (fragment_addr == base_addr) {
/* First fragment */

2
src/cpu/o3/commit_impl.hh
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@@ -701,7 +701,7 @@ DefaultCommit<Impl>::tick()
// will be active.
_nextStatus = Active;
const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
M5_VAR_USED const DynInstPtr &inst = rob->readHeadInst(tid);
DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
" ROB and ready to commit\n",

2
src/cpu/o3/lsq_impl.hh
View File

@@ -682,7 +682,7 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
// This comming request can be either load, store or atomic.
// Atomic request has a corresponding pointer to its atomic memory
// operation
bool isAtomic M5_VAR_USED = !isLoad && amo_op;
M5_VAR_USED bool isAtomic = !isLoad && amo_op;
ThreadID tid = cpu->contextToThread(inst->contextId());
auto cacheLineSize = cpu->cacheLineSize();

2
src/cpu/o3/mem_dep_unit_impl.hh
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@@ -270,7 +270,7 @@ MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
} else {
// Otherwise make the instruction dependent on the store/barrier.
DPRINTF(MemDepUnit, "Adding to dependency list\n");
for (auto M5_VAR_USED producing_store : producing_stores)
for (M5_VAR_USED auto producing_store : producing_stores)
DPRINTF(MemDepUnit, "\tinst PC %s is dependent on [sn:%lli].\n",
inst->pcState(), producing_store);

2
src/cpu/o3/scoreboard.hh
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@@ -57,7 +57,7 @@ class Scoreboard
std::vector<bool> regScoreBoard;
/** The number of actual physical registers */
unsigned M5_CLASS_VAR_USED numPhysRegs;
M5_CLASS_VAR_USED unsigned numPhysRegs;
public:
/** Constructs a scoreboard.

2
src/cpu/pred/bpred_unit.cc
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@@ -108,7 +108,7 @@ BPredUnit::drainSanityCheck() const
{
// We shouldn't have any outstanding requests when we resume from
// a drained system.
for (const auto& ph M5_VAR_USED : predHist)
for (M5_VAR_USED const auto& ph : predHist)
assert(ph.empty());
}

2
src/cpu/simple/timing.cc
View File

@@ -947,7 +947,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// hardware transactional memory
SimpleExecContext *t_info = threadInfo[curThread];
const bool is_htm_speculative M5_VAR_USED =
M5_VAR_USED const bool is_htm_speculative =
t_info->inHtmTransactionalState();
// received a response from the dcache: complete the load or store

2
src/cpu/testers/memtest/memtest.cc
View File

@@ -245,7 +245,7 @@ MemTest::tick()
if (cmd < percentReads) {
// start by ensuring there is a reference value if we have not
// seen this address before
uint8_t M5_VAR_USED ref_data = 0;
M5_VAR_USED uint8_t ref_data = 0;
auto ref = referenceData.find(req->getPaddr());
if (ref == referenceData.end()) {
referenceData[req->getPaddr()] = 0;

4
src/cpu/trace/trace_cpu.cc
View File

@@ -811,7 +811,7 @@ TraceCPU::ElasticDataGen::printReadyList() {
DPRINTF(TraceCPUData, "Printing readyList:\n");
while (itr != readyList.end()) {
auto graph_itr = depGraph.find(itr->seqNum);
GraphNode* node_ptr M5_VAR_USED = graph_itr->second;
M5_VAR_USED GraphNode* node_ptr = graph_itr->second;
DPRINTFR(TraceCPUData, "\t%lld(%s), %lld\n", itr->seqNum,
node_ptr->typeToStr(), itr->execTick);
itr++;
@@ -1341,7 +1341,7 @@ TraceCPU::ElasticDataGen::GraphNode::removeDepOnInst(NodeSeqNum done_seq_num)
// If it is not an rob dependency then it must be a register dependency
// If the register dependency is not found, it violates an assumption
// and must be caught by assert.
bool regdep_found M5_VAR_USED = removeRegDep(done_seq_num);
M5_VAR_USED bool regdep_found = removeRegDep(done_seq_num);
assert(regdep_found);
}
// Return true if the node is dependency free