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misc: Update attribute syntax, and reorganize compiler.hh.

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This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-09-26 18:26:02 -07:00
parent 3c31a214b6
commit b877efa6d4
78 changed files with 242 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/arm/faults.cc
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@@ -517,7 +517,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
saved_cpsr.v = tc->readCCReg(CCREG_V);
saved_cpsr.ge = tc->readCCReg(CCREG_GE);
Addr curPc M5_VAR_USED = tc->pcState().pc();
M5_VAR_USED Addr curPc = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
saved_cpsr.it2 = it.top6;
saved_cpsr.it1 = it.bottom2;
@@ -525,7 +525,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// if we have a valid instruction then use it to annotate this fault with
// extra information. This is used to generate the correct fault syndrome
// information
ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
// Ensure Secure state if initially in Monitor mode
if (have_security && saved_cpsr.mode == MODE_MON) {
@@ -703,7 +703,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
// If we have a valid instruction then use it to annotate this fault with
// extra information. This is used to generate the correct fault syndrome
// information
ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst);
M5_VAR_USED ArmStaticInst *arm_inst = instrAnnotate(inst);
// Set PC to start of exception handler
Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL, true);
@@ -755,7 +755,7 @@ Reset::getVector(ThreadContext *tc)
Addr base;
// Check for invalid modes
CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
M5_VAR_USED CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
@@ -1069,7 +1069,7 @@ AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// See ARM ARM B3-1416
bool override_LPAE = false;
TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
M5_VAR_USED TTBCR ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
if (ttbcr_s.eae) {
override_LPAE = true;
} else {

4
src/arch/arm/insts/macromem.cc
View File

@@ -561,7 +561,7 @@ VldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst,
unsigned eBytes = (1 << size);
unsigned loadSize = eBytes * elems;
unsigned loadRegs M5_VAR_USED =
M5_VAR_USED unsigned loadRegs =
(loadSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
assert(loadRegs > 0 && loadRegs <= 4);
@@ -925,7 +925,7 @@ VstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst,
unsigned eBytes = (1 << size);
unsigned storeSize = eBytes * elems;
unsigned storeRegs M5_VAR_USED =
M5_VAR_USED unsigned storeRegs =
(storeSize + sizeof(uint32_t) - 1) / sizeof(uint32_t);
assert(storeRegs > 0 && storeRegs <= 4);

12
src/arch/arm/isa/insts/data64.isa
View File

@@ -83,16 +83,16 @@ let {{
"logic": '0'
}
immOp2 = "uint64_t secOp M5_VAR_USED = imm;"
sRegOp2 = "uint64_t secOp M5_VAR_USED = " + \
immOp2 = "M5_VAR_USED uint64_t secOp = imm;"
sRegOp2 = "M5_VAR_USED uint64_t secOp = " + \
"shiftReg64(Op264, shiftAmt, shiftType, intWidth);"
eRegOp2 = "uint64_t secOp M5_VAR_USED = " + \
eRegOp2 = "M5_VAR_USED uint64_t secOp = " + \
"extendReg64(Op264, extendType, shiftAmt, intWidth);"
def buildDataWork(mnem, code, flagType, suffix, buildCc, buildNonCc,
base, templateBase):
code = '''
uint64_t resTemp M5_VAR_USED = 0;
M5_VAR_USED uint64_t resTemp = 0;
''' + code
ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
Name = mnem.capitalize() + suffix
@@ -576,9 +576,9 @@ let {{
def condCompCode(flagType, op, imm):
ccCode = createCcCode64(carryCode64[flagType], overflowCode64[flagType])
opDecl = "uint64_t secOp M5_VAR_USED = imm;"
opDecl = "M5_VAR_USED uint64_t secOp = imm;"
if not imm:
opDecl = "uint64_t secOp M5_VAR_USED = Op264;"
opDecl = "M5_VAR_USED uint64_t secOp = Op264;"
return opDecl + '''
if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)) {
uint64_t resTemp = Op164 ''' + op + ''' secOp;

4
src/arch/arm/isa/insts/fp.isa
View File

@@ -461,7 +461,7 @@ let {{
exec_output = ""
singleSimpleCode = vfpEnabledCheckCode + '''
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
FpDest = %(op)s;
'''
singleCode = singleSimpleCode + '''
@@ -482,7 +482,7 @@ let {{
"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
doubleCode = vfpEnabledCheckCode + '''
FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
M5_VAR_USED FPSCR fpscr = (FPSCR) FpscrExc;
double dest = %(op)s;
FpDestP0_uw = dblLow(dest);
FpDestP1_uw = dblHi(dest);

2
src/arch/arm/isa/insts/ldr64.isa
View File

@@ -201,7 +201,7 @@ let {{
accEpilogCode = None
# Code that actually handles the access
if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
accCode = 'M5_VAR_USED uint64_t temp = Mem%s;'
elif self.flavor == "fp":
accEpilogCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,

2
src/arch/arm/isa/insts/misc64.isa
View File

@@ -128,7 +128,7 @@ let {{
bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1));
diff += intWidth;
}
uint64_t topBits M5_VAR_USED = ~mask(diff+1);
M5_VAR_USED uint64_t topBits = ~mask(diff+1);
uint64_t result = imm1 == 0 ? Op164 :
(Op164 >> imm1) | (Op164 << (intWidth - imm1));
result &= bitMask;

4
src/arch/arm/isa/insts/sve.isa
View File

@@ -2703,7 +2703,7 @@ let {{
CondCodesC = !destPred.lastActive(GpOp, eCount);
CondCodesV = 0;'''
extraPrologCode = '''
auto& destPred M5_VAR_USED = PDest;'''
M5_VAR_USED auto& destPred = PDest;'''
baseClass = ('SvePredUnaryWImplicitSrcOp' if predType == PredType.NONE
else 'SvePredUnaryWImplicitSrcPredOp')
iop = InstObjParams(name, 'Sve' + Name, baseClass,
@@ -2722,7 +2722,7 @@ let {{
global header_output, exec_output, decoders
code = sveEnabledCheckCode + op
extraPrologCode = '''
auto& destPred M5_VAR_USED = Ffr;'''
M5_VAR_USED auto& destPred = Ffr;'''
baseClass = ('SveWImplicitSrcDstOp' if isSetFfr
else 'SvePredUnaryWImplicitDstOp')
iop = InstObjParams(name, 'Sve' + Name, baseClass,

4
src/arch/arm/isa/templates/mem.isa
View File

@@ -1117,7 +1117,7 @@ def template LoadRegConstructor {{
(IntRegIndex)_index)
{
%(constructor)s;
bool conditional M5_VAR_USED = false;
M5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
@@ -1183,7 +1183,7 @@ def template LoadImmConstructor {{
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
bool conditional M5_VAR_USED = false;
M5_VAR_USED bool conditional = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {

38
src/arch/arm/isa/templates/sve_mem.isa
View File

@@ -142,7 +142,7 @@ def template SveContigLoadExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -176,7 +176,7 @@ def template SveContigLoadInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -200,7 +200,7 @@ def template SveContigLoadCompleteAcc {{
Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
{
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -229,7 +229,7 @@ def template SveContigStoreExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -266,7 +266,7 @@ def template SveContigStoreInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -308,7 +308,7 @@ def template SveLoadAndReplExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -339,7 +339,7 @@ def template SveLoadAndReplInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_src_decl)s;
%(op_rd)s;
@@ -363,7 +363,7 @@ def template SveLoadAndReplCompleteAcc {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<RegElemType>(
xc->tcBase());
@@ -547,7 +547,7 @@ def template SveGatherLoadMicroopExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -595,7 +595,7 @@ def template SveGatherLoadMicroopInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_src_decl)s;
%(op_rd)s;
@@ -635,7 +635,7 @@ def template SveGatherLoadMicroopCompleteAcc {{
Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
ExecContext *xc, Trace::InstRecord *traceData) const
{
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -661,7 +661,7 @@ def template SveScatterStoreMicroopExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -691,7 +691,7 @@ def template SveScatterStoreMicroopInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -759,7 +759,7 @@ def template SveFirstFaultWritebackMicroopExecute {{
Fault %(class_name)s%(tpl_args)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
%(op_decl)s;
%(op_rd)s;
@@ -933,7 +933,7 @@ def template SveStructLoadExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
@@ -965,7 +965,7 @@ def template SveStructLoadInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
@@ -989,7 +989,7 @@ def template SveStructLoadCompleteAcc {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
@@ -1021,7 +1021,7 @@ def template SveStructStoreExecute {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
@@ -1058,7 +1058,7 @@ def template SveStructStoreInitiateAcc {{
{
Addr EA;
Fault fault = NoFault;
bool aarch64 M5_VAR_USED = true;
M5_VAR_USED bool aarch64 = true;
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());

8
src/arch/arm/remote_gdb.hh
View File

@@ -66,12 +66,12 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct M5_ATTR_PACKED {
uint32_t gpr[16];
uint32_t cpsr;
uint64_t fpr[32];
uint32_t fpscr;
} M5_ATTR_PACKED r;
} r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }
@@ -88,7 +88,7 @@ class RemoteGDB : public BaseRemoteGDB
{
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
struct M5_ATTR_PACKED {
uint64_t x[31];
uint64_t spx;
uint64_t pc;
@@ -96,7 +96,7 @@ class RemoteGDB : public BaseRemoteGDB
VecElem v[NumVecV8ArchRegs * NumVecElemPerNeonVecReg];
uint32_t fpsr;
uint32_t fpcr;
} M5_ATTR_PACKED r;
} r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }

2
src/arch/arm/tlb.cc
View File

@@ -695,7 +695,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
// Cache clean operations require read permissions to the specified VA
bool is_write = !req->isCacheClean() && mode == Write;
bool is_atomic = req->isAtomic();
bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode);
M5_VAR_USED bool is_priv = isPriv && !(flags & UserMode);
updateMiscReg(tc, curTranType);

2
src/arch/isa_parser.py
View File

@@ -166,7 +166,7 @@ class Template(object):
if operands.predRead:
myDict['op_decl'] += 'uint8_t _sourceIndex = 0;\n'
if operands.predWrite:
myDict['op_decl'] += 'uint8_t M5_VAR_USED _destIndex = 0;\n'
myDict['op_decl'] += 'M5_VAR_USED uint8_t _destIndex = 0;\n'
is_src = lambda op: op.is_src
is_dest = lambda op: op.is_dest

4
src/arch/mips/interrupts.cc
View File

@@ -145,8 +145,8 @@ Interrupts::getInterrupt()
{
assert(checkInterrupts());
StatusReg M5_VAR_USED status = tc->readMiscRegNoEffect(MISCREG_STATUS);
CauseReg M5_VAR_USED cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
M5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
M5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
(unsigned)status.im, (unsigned)cause.ip);

2
src/arch/mips/isa/formats/mem.isa
View File

@@ -404,7 +404,7 @@ def template MiscExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA M5_VAR_USED = 0;
M5_VAR_USED Addr EA = 0;
Fault fault = NoFault;
%(fp_enable_check)s;

2
src/arch/mips/isa/formats/mt.isa
View File

@@ -111,7 +111,7 @@ def template ThreadRegisterExecute {{
ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
int64_t data M5_VAR_USED;
M5_VAR_USED int64_t data;
%(op_decl)s;
%(op_rd)s;

2
src/arch/power/isa/formats/mem.isa
View File

@@ -109,7 +109,7 @@ def template LoadCompleteAcc {{
ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr M5_VAR_USED EA;
M5_VAR_USED Addr EA;
Fault fault = NoFault;
%(op_decl)s;

2
src/arch/riscv/isa.cc
View File

@@ -49,7 +49,7 @@
namespace RiscvISA
{
const std::array<const char *, NumMiscRegs> M5_VAR_USED MiscRegNames = {{
M5_VAR_USED const std::array<const char *, NumMiscRegs> MiscRegNames = {{
[MISCREG_PRV] = "PRV",
[MISCREG_ISA] = "ISA",
[MISCREG_VENDORID] = "VENDORID",

2
src/arch/sparc/isa/formats/basic.isa
View File

@@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault doFpOp(ExecContext *, Trace::InstRecord *) const M5_NO_INLINE;
M5_NO_INLINE Fault doFpOp(ExecContext *, Trace::InstRecord *) const;
};
}};

4
src/arch/x86/isa/microops/regop.isa
View File

@@ -49,7 +49,7 @@ def template MicroRegOpExecute {{
%(op_decl)s;
%(op_rd)s;
RegVal result M5_VAR_USED;
M5_VAR_USED RegVal result;
if(%(cond_check)s)
{
@@ -79,7 +79,7 @@ def template MicroRegOpImmExecute {{
%(op_decl)s;
%(op_rd)s;
RegVal result M5_VAR_USED;
M5_VAR_USED RegVal result;
if(%(cond_check)s)
{

2
src/arch/x86/ldstflags.hh
View File

@@ -46,7 +46,7 @@
*/
namespace X86ISA
{
const Request::FlagsType M5_VAR_USED SegmentFlagMask = mask(4);
M5_VAR_USED const Request::FlagsType SegmentFlagMask = mask(4);
const int FlagShift = 4;
enum FlagBit {
CPL0FlagBit = 1,