derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-vega: Implement ds_add_u64

Browse Source 
This instruction does an atomic add of an unsigned 64-bit data with a
VGPR and value in LDS atomically without return.

Change-Id: I6a7d6713b256607c4e69ddbdef5c83172493c077
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67075
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2022-12-26 09:54:20 -08:00
parent 892e3057f7
commit b83457df0b
2 changed files with 48 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
src/arch/amdgpu/vega/insts/instructions.cc
View File

@@ -36088,6 +36088,10 @@ namespace VegaISA
Inst_DS__DS_ADD_U64::Inst_DS__DS_ADD_U64(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_add_u64")
{
setFlag(MemoryRef);
setFlag(GroupSegment);
setFlag(AtomicAdd);
setFlag(AtomicNoReturn);
} // Inst_DS__DS_ADD_U64
Inst_DS__DS_ADD_U64::~Inst_DS__DS_ADD_U64()
@@ -36096,14 +36100,53 @@ namespace VegaISA
// --- description from .arch file ---
// 64b:
// tmp = MEM[ADDR];
// MEM[ADDR] += DATA[0:1];
// RETURN_DATA[0:1] = tmp.
void
Inst_DS__DS_ADD_U64::execute(GPUDynInstPtr gpuDynInst)
{
panicUnimplemented();
Wavefront *wf = gpuDynInst->wavefront();
if (gpuDynInst->exec_mask.none()) {
wf->decLGKMInstsIssued();
return;
}
gpuDynInst->execUnitId = wf->execUnitId;
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(
gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU64 data(gpuDynInst, extData.DATA0);
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
(reinterpret_cast<VecElemU64*>(gpuDynInst->a_data))[lane]
= data[lane];
}
}
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
void
Inst_DS__DS_ADD_U64::initiateAcc(GPUDynInstPtr gpuDynInst)
{
Addr offset0 = instData.OFFSET0;
Addr offset1 = instData.OFFSET1;
Addr offset = (offset1 << 8) | offset0;
initAtomicAccess<VecElemU64>(gpuDynInst, offset);
} // initiateAcc
void
Inst_DS__DS_ADD_U64::completeAcc(GPUDynInstPtr gpuDynInst)
{
} // completeAcc
// --- Inst_DS__DS_SUB_U64 class methods ---
Inst_DS__DS_SUB_U64::Inst_DS__DS_SUB_U64(InFmt_DS *iFmt)

2
src/arch/amdgpu/vega/insts/instructions.hh
View File

@@ -33079,6 +33079,8 @@ namespace VegaISA
}
} // getOperandSize
void initiateAcc(GPUDynInstPtr gpuDynInst) override;
void completeAcc(GPUDynInstPtr gpuDynInst) override;
void execute(GPUDynInstPtr) override;
}; // Inst_DS__DS_ADD_U64