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cpu,stdlib: Updating strided generator (#762)

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This change improves the functionality of strided generator to create
trace with better flexibility.
It allows the user to manually set offset and stride size instead of
calculating it based on a "gen_id".
This way different patterns could be created with the same SimObject.
In addition, this change adds stdlib components for strided generator.
This commit is contained in:
Mahyar Samani
2024-02-01 09:08:42 -08:00
committed by GitHub
parent b5fae2f620
commit b79fe82e5c
8 changed files with 299 additions and 49 deletions
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4
src/python/SConscript
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@@ -241,6 +241,10 @@ PySource('gem5.components.processors',
'gem5/components/processors/linear_generator_core.py')
PySource('gem5.components.processors',
'gem5/components/processors/linear_generator.py')
PySource('gem5.components.processors',
'gem5/components/processors/strided_generator_core.py')
PySource('gem5.components.processors',
'gem5/components/processors/strided_generator.py')
PySource('gem5.components.processors',
'gem5/components/processors/random_generator_core.py')
PySource('gem5.components.processors',

101
src/python/gem5/components/processors/strided_generator.py Normal file
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@@ -0,0 +1,101 @@
# Copyright (c) 2023 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import (
List,
Optional,
)
from gem5.components.processors.abstract_generator import AbstractGenerator
from gem5.utils.override import overrides
from .strided_generator_core import StridedGeneratorCore
class StridedGenerator(AbstractGenerator):
def __init__(
self,
num_cores: int = 1,
duration: str = "1ms",
rate: str = "100GB/s",
block_size: int = 64,
superblock_size: int = 64,
stride_size: Optional[int] = None,
min_addr: int = 0,
max_addr: int = 32768,
rd_perc: int = 100,
data_limit: int = 0,
) -> None:
if stride_size is None:
stride_size = num_cores * superblock_size
super().__init__(
cores=self._create_cores(
num_cores=num_cores,
duration=duration,
rate=rate,
block_size=block_size,
superblock_size=superblock_size,
stride_size=stride_size,
min_addr=min_addr,
max_addr=max_addr,
rd_perc=rd_perc,
data_limit=data_limit,
)
)
def _create_cores(
self,
num_cores: int,
duration: str,
rate: str,
block_size: int,
superblock_size: int,
stride_size: int,
min_addr: int,
max_addr: int,
rd_perc: int,
data_limit: int,
) -> List[StridedGeneratorCore]:
return [
StridedGeneratorCore(
duration=duration,
rate=rate,
block_size=block_size,
superblock_size=superblock_size,
stride_size=stride_size,
min_addr=min_addr,
max_addr=max_addr,
offset=i * superblock_size,
rd_perc=rd_perc,
data_limit=data_limit,
)
for i in range(num_cores)
]
@overrides(AbstractGenerator)
def start_traffic(self) -> None:
for core in self.cores:
core.start_traffic()

106
src/python/gem5/components/processors/strided_generator_core.py Normal file
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@@ -0,0 +1,106 @@
# Copyright (c) 2023 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import Iterator
from m5.objects import (
BaseTrafficGen,
Port,
PyTrafficGen,
)
from m5.ticks import fromSeconds
from m5.util.convert import (
toLatency,
toMemoryBandwidth,
)
from gem5.components.processors.abstract_core import AbstractCore
from gem5.components.processors.abstract_generator_core import (
AbstractGeneratorCore,
)
from gem5.utils.override import overrides
class StridedGeneratorCore(AbstractGeneratorCore):
def __init__(
self,
duration: str,
rate: str,
block_size: int,
superblock_size: int,
stride_size: int,
min_addr: int,
max_addr: int,
offset: int,
rd_perc: int,
data_limit: int,
) -> None:
super().__init__()
self.generator = PyTrafficGen()
self._duration = duration
self._rate = rate
self._block_size = block_size
self._superblock_size = superblock_size
self._stride_size = stride_size
self._min_addr = min_addr
self._max_addr = max_addr
self._offset = offset
self._rd_perc = rd_perc
self._data_limit = data_limit
@overrides(AbstractCore)
def connect_dcache(self, port: Port) -> None:
self.generator.port = port
def _set_traffic(self) -> None:
self._traffic = self._create_traffic()
def _create_traffic(self) -> Iterator[BaseTrafficGen]:
duration = fromSeconds(toLatency(self._duration))
rate = toMemoryBandwidth(self._rate)
period = fromSeconds(self._block_size / rate)
min_period = period
max_period = period
yield self.generator.createStrided(
duration,
self._min_addr,
self._max_addr,
self._offset,
self._block_size,
self._superblock_size,
self._stride_size,
min_period,
max_period,
self._rd_perc,
self._data_limit,
)
yield self.generator.createExit(0)
@overrides(AbstractGeneratorCore)
def start_traffic(self) -> None:
self._set_traffic()
self.generator.start(self._traffic)