dev-amdgpu: Add GPU interrupt handler object
Add device interrupt handler for amdgpu device. The interrupt handler is primarily used to signal that fences in the kernel driver can be passed. Change-Id: I574fbfdef6e3bae310ec7f86058811e1e4886df6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51849 Maintainer: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
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Matthew Poremba
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src/dev/amdgpu/interrupt_handler.hh
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176
src/dev/amdgpu/interrupt_handler.hh
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/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __DEV_AMDGPU_INTERRUPT_HANDLER__
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#define __DEV_AMDGPU_INTERRUPT_HANDLER__
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#include <bitset>
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#include <iostream>
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#include <queue>
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#include <vector>
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#include "base/addr_range.hh"
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#include "base/flags.hh"
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#include "base/types.hh"
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#include "dev/amdgpu/amdgpu_device.hh"
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#include "dev/dma_device.hh"
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#include "params/AMDGPUInterruptHandler.hh"
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namespace gem5
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{
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/*
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* MSI-style interrupts. Send a "cookie" response to clear interrupts.
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* From [1] we know the size of the struct is 8 dwords. Then we can look at
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* the register shift offsets in [2] to guess the rest. Or we can also look
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* at [3].
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*
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* [1] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/amdkfd/kfd_device.c#L316
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* [2] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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* drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h#L122
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* [3] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/
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drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h#L46
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*
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*/
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typedef struct
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{
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uint32_t clientId : 8;
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uint32_t sourceId : 8;
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uint32_t ringId : 8;
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uint32_t vmId : 4;
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uint32_t reserved1 : 3;
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uint32_t vmid_type : 1;
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uint32_t timestamp_Lo;
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uint32_t timestamp_Hi : 16;
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uint32_t reserved2 : 15;
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uint32_t timestamp_src : 1;
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uint32_t pasid : 16;
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uint32_t reserved3 : 15;
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uint32_t pasid_src : 1;
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uint32_t source_data_dw1;
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uint32_t source_data_dw2;
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uint32_t source_data_dw3;
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uint32_t source_data_dw4;
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} AMDGPUInterruptCookie;
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typedef struct
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{
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uint32_t IH_Cntl;
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uint32_t IH_Base;
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uint32_t IH_Base_Hi;
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Addr baseAddr;
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uint32_t IH_Rptr;
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uint32_t IH_Wptr;
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uint32_t IH_Wptr_Addr_Lo;
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uint32_t IH_Wptr_Addr_Hi;
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Addr WptrAddr;
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uint32_t IH_Doorbell;
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} AMDGPUIHRegs;
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constexpr uint32_t INTR_COOKIE_SIZE = 32; // in bytes
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class AMDGPUInterruptHandler : public DmaDevice
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{
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public:
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class DmaEvent : public Event
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{
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private:
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AMDGPUInterruptHandler *deviceIh;
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uint32_t data;
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public:
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DmaEvent(AMDGPUInterruptHandler *deviceIh, uint32_t data)
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: Event(), deviceIh(deviceIh), data(data)
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{
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setFlags(Event::AutoDelete);
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}
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void process();
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const char *description() const {
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return "AMDGPUInterruptHandler Dma";
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}
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void setData(uint32_t _data) { data = _data; }
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uint32_t getData() { return data; }
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};
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struct SenderState : public Packet::SenderState
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{
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SenderState(Packet::SenderState *sender_state, Addr addr)
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: saved(sender_state), _addr(addr)
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{
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}
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Packet::SenderState *saved;
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Addr _addr;
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};
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AMDGPUInterruptHandler(const AMDGPUInterruptHandlerParams &p);
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Tick write(PacketPtr pkt) override { return 0; }
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Tick read(PacketPtr pkt) override { return 0; }
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AddrRangeList getAddrRanges() const override;
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void setGPUDevice(AMDGPUDevice *gpu_device) { gpuDevice = gpu_device; }
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void prepareInterruptCookie(ContextID cntxtId, uint32_t ring_id,
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uint32_t client_id, uint32_t source_id);
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void submitInterruptCookie();
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void submitWritePointer();
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void intrPost();
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/**
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* Methods for setting the values of interrupt handler MMIO registers.
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*/
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void writeMMIO(PacketPtr pkt, Addr mmio_offset);
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uint32_t getDoorbellOffset() const { return regs.IH_Doorbell; }
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void setCntl(const uint32_t &data);
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void setBase(const uint32_t &data);
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void setBaseHi(const uint32_t &data);
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void setRptr(const uint32_t &data);
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void setWptr(const uint32_t &data);
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void setWptrAddrLo(const uint32_t &data);
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void setWptrAddrHi(const uint32_t &data);
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void setDoorbellOffset(const uint32_t &data);
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void updateRptr(const uint32_t &data);
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private:
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AMDGPUDevice *gpuDevice;
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AMDGPUIHRegs regs;
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std::queue<AMDGPUInterruptCookie*> interruptQueue;
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AMDGPUInterruptHandler::DmaEvent *dmaEvent;
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};
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} // namespace gem5
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#endif // __DEV_AMDGPU_INTERRUPT_HANDLER__
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