derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dev-amdgpu: Add GPU interrupt handler object

Browse Source 
Add device interrupt handler for amdgpu device. The interrupt handler is
primarily used to signal that fences in the kernel driver can be passed.

Change-Id: I574fbfdef6e3bae310ec7f86058811e1e4886df6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51849
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2021-10-20 15:20:59 -05:00
parent 8da24ea088
commit b7826f1329
7 changed files with 622 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
src/dev/amdgpu/amdgpu_device.hh
View File

@@ -44,6 +44,8 @@
namespace gem5
{
class AMDGPUInterruptHandler;
/**
* Device model for an AMD GPU. This models the interface between the PCI bus
* and the various IP blocks behind it. It translates requests to the various
@@ -76,6 +78,14 @@ class AMDGPUDevice : public PciDevice
void writeDoorbell(PacketPtr pkt, Addr offset);
void writeMMIO(PacketPtr pkt, Addr offset);
/**
* Structures to hold registers, doorbells, and some frame memory
*/
using GPURegMap = std::unordered_map<uint32_t, uint64_t>;
GPURegMap frame_regs;
GPURegMap regs;
std::unordered_map<uint32_t, QueueType> doorbells;
/**
* VGA ROM methods
*/
@@ -91,10 +101,13 @@ class AMDGPUDevice : public PciDevice
AMDMMIOReader mmioReader;
/**
* Device registers - Maps register address to register value
* Blocks of the GPU
*/
std::unordered_map<uint32_t, uint64_t> regs;
AMDGPUInterruptHandler *deviceIH;
/**
* Initial checkpoint support variables.
*/
bool checkpoint_before_mmios;
int init_interrupt_count;
@@ -185,6 +198,41 @@ class AMDGPUDevice : public PciDevice
assert(vmid > 0 && vmid < vmContexts.size());
return vmContexts[vmid].ptStart;
}
Addr
getMmioAperture(Addr addr)
{
// Aperture ranges:
// NBIO 0x0 - 0x4280
// IH 0x4280 - 0x4980
// SDMA0 0x4980 - 0x5180
// SDMA1 0x5180 - 0x5980
// GRBM 0x8000 - 0xD000
// GFX 0x28000 - 0x3F000
// MMHUB 0x68000 - 0x6a120
if (IH_BASE <= addr && addr < IH_BASE + IH_SIZE)
return IH_BASE;
else if (SDMA0_BASE <= addr && addr < SDMA0_BASE + SDMA_SIZE)
return SDMA0_BASE;
else if (SDMA1_BASE <= addr && addr < SDMA1_BASE + SDMA_SIZE)
return SDMA1_BASE;
else if (GRBM_BASE <= addr && addr < GRBM_BASE + GRBM_SIZE)
return GRBM_BASE;
else if (GFX_BASE <= addr && addr < GFX_BASE + GFX_SIZE)
return GFX_BASE;
else if (MMHUB_BASE <= addr && addr < MMHUB_BASE + MMHUB_SIZE)
return MMHUB_BASE;
else {
warn_once("Accessing unsupported MMIO aperture! Assuming NBIO\n");
return NBIO_BASE;
}
}
/**
* Setters to set values from other GPU blocks.
*/
void setDoorbellType(uint32_t offset, QueueType qt);
};
} // namespace gem5