diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 0966ca80d2..9cf8e8de19 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -41,11 +41,13 @@
 #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
 #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
 
+#include <type_traits>
 #include <unordered_map>
 
 #include "base/compiler.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/protocol/AccessPermission.hh"
+#include "mem/ruby/system/RubySystem.hh"
 
 namespace gem5
 {
@@ -74,7 +76,7 @@ class PerfectCacheMemory
   public:
     PerfectCacheMemory();
 
-    void setBlockSize(const int block_size) { m_block_size = block_size; }
+    void setRubySystem(RubySystem *rs);
 
     // tests to see if an address is present in the cache
     bool isTagPresent(Addr address) const;
@@ -111,7 +113,11 @@ class PerfectCacheMemory
     // Data Members (m_prefix)
     std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
 
+    RubySystem *m_ruby_system = nullptr;
     int m_block_size = 0;
+
+    static constexpr bool entryRequiresRubySystem =
+        std::is_member_function_pointer_v<decltype(&ENTRY::setRubySystem)>;
 };
 
 template<class ENTRY>
@@ -129,6 +135,14 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
 {
 }
 
+template<class ENTRY>
+inline
+void PerfectCacheMemory<ENTRY>::setRubySystem(RubySystem *rs)
+{
+    m_ruby_system = rs;
+    m_block_size = rs->getBlockSizeBytes();
+}
+
 // tests to see if an address is present in the cache
 template<class ENTRY>
 inline bool
@@ -153,6 +167,9 @@ PerfectCacheMemory<ENTRY>::allocate(Addr address)
     PerfectCacheLineState<ENTRY> line_state;
     line_state.m_permission = AccessPermission_Invalid;
     line_state.m_entry = ENTRY();
+    if constexpr (entryRequiresRubySystem) {
+        line_state.m_entry.setRubySystem(m_ruby_system);
+    }
     Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
     m_map.emplace(line_addr, line_state);
 }
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 42f4c332d2..c1052086bf 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -833,11 +833,11 @@ $c_ident::init()
 
                     # For objects that require knowing the cache line size,
                     # set the value here.
-                    if vtype.c_ident in ("TBETable", "PerfectCacheMemory"):
+                    if vtype.c_ident in ("TBETable"):
                         block_size_func = "m_ruby_system->getBlockSizeBytes()"
                         code(f"(*{vid}).setBlockSize({block_size_func});")
 
-                    if vtype.c_ident in ("NetDest"):
+                    if vtype.c_ident in ("NetDest", "PerfectCacheMemory"):
                         code(f"(*{vid}).setRubySystem(m_ruby_system);")
 
         for param in self.config_parameters: