diff --git a/src/dev/amdgpu/interrupt_handler.cc b/src/dev/amdgpu/interrupt_handler.cc index 46c6979fef..585c1cfc04 100644 --- a/src/dev/amdgpu/interrupt_handler.cc +++ b/src/dev/amdgpu/interrupt_handler.cc @@ -77,6 +77,12 @@ AMDGPUInterruptHandler::prepareInterruptCookie(ContextID cntxt_id, uint32_t client_id, uint32_t source_id) { + assert(client_id == SOC15_IH_CLIENTID_RLC || + client_id == SOC15_IH_CLIENTID_SDMA0 || + client_id == SOC15_IH_CLIENTID_SDMA1 || + client_id == SOC15_IH_CLIENTID_GRBM_CP); + assert(source_id == CP_EOP || source_id == TRAP_ID); + /** * Setup the fields in the interrupt cookie (see header file for more * detail on the fields). The timestamp here is a bogus value. It seems diff --git a/src/dev/amdgpu/interrupt_handler.hh b/src/dev/amdgpu/interrupt_handler.hh index 5e5175fbbe..ab8a853074 100644 --- a/src/dev/amdgpu/interrupt_handler.hh +++ b/src/dev/amdgpu/interrupt_handler.hh @@ -57,11 +57,13 @@ enum soc15_ih_clientid { SOC15_IH_CLIENTID_RLC = 0x07, SOC15_IH_CLIENTID_SDMA0 = 0x08, - SOC15_IH_CLIENTID_SDMA1 = 0x09 + SOC15_IH_CLIENTID_SDMA1 = 0x09, + SOC15_IH_CLIENTID_GRBM_CP = 0x14 }; enum ihSourceId { + CP_EOP = 181, TRAP_ID = 224 }; diff --git a/src/dev/amdgpu/pm4_packet_processor.cc b/src/dev/amdgpu/pm4_packet_processor.cc index 1213ce60ad..67c150a3a2 100644 --- a/src/dev/amdgpu/pm4_packet_processor.cc +++ b/src/dev/amdgpu/pm4_packet_processor.cc @@ -499,7 +499,7 @@ PM4PacketProcessor::releaseMemDone(PM4Queue *q, PM4ReleaseMem *pkt, Addr addr) // format specified in PM4ReleaseMem pkt. uint32_t ringId = (q->me() << 6) | (q->pipe() << 4) | q->queue(); gpuDevice->getIH()->prepareInterruptCookie(pkt->intCtxId, ringId, - SOC15_IH_CLIENTID_RLC, TRAP_ID); + SOC15_IH_CLIENTID_GRBM_CP, CP_EOP); gpuDevice->getIH()->submitInterruptCookie(); }