arm,stdlib: added kvm support to the ARM board (#725)
This change adds support to use KVM cores on the ARM board. The board simulates gic to enable KVM, similar to the gem5 ARM FS configs. The limitation is that it only supports VExpress_GEM5_V1. Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
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@@ -42,6 +42,7 @@ from m5.objects import (
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BadAddr,
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Bridge,
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CowDiskImage,
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GenericTimer,
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IOXBar,
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PciVirtIO,
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Port,
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@@ -51,6 +52,7 @@ from m5.objects import (
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Terminal,
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VExpress_GEM5_Base,
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VExpress_GEM5_Foundation,
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VExpress_GEM5_V1,
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VirtIOBlock,
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VncServer,
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VoltageDomain,
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@@ -80,6 +82,7 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
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**Limitations**
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* stage2 walker ports are ignored.
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* KVM cores only work with VExpress_GEM5_V1
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"""
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__metaclass__ = ABCMeta
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@@ -110,8 +113,13 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
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requires(isa_required=ISA.ARM)
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# Setting up ARM release here. We use the ARM default release, which
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# corresponds to an ARMv8 system.
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# corresponds to an ARMv8 system. The default release is updated if
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# the user is using any KVM cores.
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self.release = release
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if any(core.is_kvm_core() for core in processor.get_cores()):
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# KVM cores only work with VExpress_GEM5_V1()
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if isinstance(platform, VExpress_GEM5_V1):
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self.release = ArmDefaultRelease.for_kvm()
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# Setting multi_proc of ArmSystem by counting the number of processors.
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if processor.get_num_cores() == 1:
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@@ -211,6 +219,17 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
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if hasattr(self.realview.gic, "cpu_addr"):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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# For KVM cpus, we need to simulate the GIC.
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if any(core.is_kvm_core() for core in self.processor.get_cores()):
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# The following is taken from
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# `tests/fs/linux/arm/configs/arm_generic.py`:
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# Arm KVM regressions will use a simulated GIC. This means that in
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# order to work we need to remove the system interface of the
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# generic timer from the DTB and we need to inform the MuxingKvmGic
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# class to use the gem5 GIC instead of relying on the host one
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GenericTimer.generateDeviceTree = SimObject.generateDeviceTree
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self.realview.gic.simulate_gic = True
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# IO devices has to setup before incorporating the caches in the case
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# of ruby caches. Otherwise the DMA controllers are incorrectly
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# created. The IO device has to be attached first. This is done in the
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