From b51927e7a8fd88feb2c3959538928c8cf20deeb6 Mon Sep 17 00:00:00 2001
From: Alexander Richardson <alexrichardson@google.com>
Date: Mon, 29 Jul 2024 08:57:48 -0700
Subject: [PATCH] arch-arm: return 64-bit cycle counter for MISCREG_PMCCNTR
 (#1390)

In AArch32 mode it is possible to read a 64-bit counter using mrrc.
Instead of truncating in the PMU code, just allow the instruction
implementation to truncate to 32 bits if accessed using mrc.

Change-Id: I77620f6d1852a7d9e79c1ecee50f4297b4103b1c
---
 src/arch/arm/pmu.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 2cb7085ca2..7e425ba08b 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -349,10 +349,8 @@ PMU::readMiscRegInt(int misc_reg)
         return reg_pmceid1 & 0xFFFFFFFF;
 
       case MISCREG_PMCCNTR_EL0:
-        return cycleCounter.getValue();
-
       case MISCREG_PMCCNTR:
-        return cycleCounter.getValue() & 0xFFFFFFFF;
+        return cycleCounter.getValue();
 
       case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
         return getCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0);