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arch-vega, gpu-compute: Add vectors to hold op info

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This removes the need for redundant functions like
isScalarRegister/isVectorRegister, as well as
isSrcOperand/isDstOperand. Also, the op info is only
generated once this way instead of every time it's needed.

Change-Id: I8af5080502ed08ed9107a441e2728828f86496f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42211
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Kyle Roarty
2019-07-09 16:25:32 -04:00
committed by Matt Sinclair
parent 0e2564a629
commit b40b361bee
11 changed files with 1233 additions and 80257 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh
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@@ -63,18 +63,9 @@ namespace Gcn3ISA
return isExecMask(opIdx);
}
bool isScalarRegister(int opIdx) override { return false; }
bool isVectorRegister(int opIdx) override { return false; }
bool isSrcOperand(int opIdx) override { return false; }
bool isDstOperand(int opIdx) override { return false; }
void initOperandInfo() override { return; }
int getOperandSize(int opIdx) override { return 0; }
int
getRegisterIndex(int opIdx, int num_scalar_regs) override
{
return 0;
}
/**
* Return the number of tokens needed by the coalescer. In GCN3 there
* is generally one packet per memory request per lane generated. In

38948
src/arch/amdgpu/gcn3/insts/instructions.hh
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File diff suppressed because it is too large Load Diff

1640
src/arch/amdgpu/gcn3/insts/op_encodings.cc
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File diff suppressed because it is too large Load Diff

59
src/arch/amdgpu/gcn3/insts/op_encodings.hh
View File

@@ -77,9 +77,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -101,9 +99,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -125,9 +121,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -149,9 +143,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -173,9 +165,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -191,9 +181,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
/**
@@ -274,9 +262,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -298,9 +284,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -322,9 +306,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -359,9 +341,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -393,9 +373,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -416,9 +394,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>
@@ -516,9 +492,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>
@@ -724,6 +698,7 @@ namespace Gcn3ISA
~Inst_MTBUF();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -742,6 +717,7 @@ namespace Gcn3ISA
~Inst_MIMG();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -757,6 +733,7 @@ namespace Gcn3ISA
~Inst_EXP();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -774,9 +751,7 @@ namespace Gcn3ISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>

11
src/arch/amdgpu/vega/insts/gpu_static_inst.hh
View File

@@ -57,18 +57,9 @@ namespace VegaISA
return isFlatScratchReg(opIdx);
}
bool isScalarRegister(int opIdx) override { return false; }
bool isVectorRegister(int opIdx) override { return false; }
bool isSrcOperand(int opIdx) override { return false; }
bool isDstOperand(int opIdx) override { return false; }
void initOperandInfo() override { return; }
int getOperandSize(int opIdx) override { return 0; }
int
getRegisterIndex(int opIdx, int num_scalar_regs) override
{
return 0;
}
/**
* Return the number of tokens needed by the coalescer. In VEGA there
* is generally one packet per memory request per lane generated. In

38948
src/arch/amdgpu/vega/insts/instructions.hh
View File

File diff suppressed because it is too large Load Diff

1636
src/arch/amdgpu/vega/insts/op_encodings.cc
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File diff suppressed because it is too large Load Diff

59
src/arch/amdgpu/vega/insts/op_encodings.hh
View File

@@ -77,9 +77,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -101,9 +99,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -125,9 +121,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -149,9 +143,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -173,9 +165,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -191,9 +181,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
/**
@@ -274,9 +262,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -298,9 +284,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -322,9 +306,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -359,9 +341,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -393,9 +373,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -416,9 +394,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>
@@ -516,9 +492,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>
@@ -723,6 +697,7 @@ namespace VegaISA
~Inst_MTBUF();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -741,6 +716,7 @@ namespace VegaISA
~Inst_MIMG();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -756,6 +732,7 @@ namespace VegaISA
~Inst_EXP();
int instSize() const override;
void initOperandInfo() override;
protected:
// first instruction DWORD
@@ -773,9 +750,7 @@ namespace VegaISA
int instSize() const override;
void generateDisassembly() override;
bool isScalarRegister(int opIdx) override;
bool isVectorRegister(int opIdx) override;
int getRegisterIndex(int opIdx, int num_scalar_regs) override;
void initOperandInfo() override;
protected:
template<typename T>