derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

CPU: Moving towards a more general port across CPU models

Browse Source 
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
This commit is contained in:
Andreas Hansson
2012-01-17 12:55:08 -06:00
parent f85286b3de
commit b3f930c884
18 changed files with 409 additions and 402 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/cpu/BaseCPU.py
View File

@@ -152,9 +152,12 @@ class BaseCPU(MemObject):
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
_cached_ports = []
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
_cached_ports = ["itb.walker.port", "dtb.walker.port"]
_cached_ports += ["itb.walker.port", "dtb.walker.port"]
_uncached_ports = []
if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: