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Implement a very very simple bus

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requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
This commit is contained in:
Ali Saidi
2006-03-25 18:31:20 -05:00
parent a70ce910f3
commit b38f67d5b7
11 changed files with 196 additions and 23 deletions
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7
python/m5/objects/Bus.py
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@@ -1,7 +1,6 @@
from m5 import *
from BaseHier import BaseHier
from MemObject import MemObject
class Bus(BaseHier):
class Bus(MemObject):
type = 'Bus'
clock = Param.Clock("bus frequency")
width = Param.Int("bus width in bytes")
bus_id = Param.Int(0, "blah")