From b355baac939ef7ec7aafec3b707afd577ff923e4 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 31 May 2023 13:57:12 +0100
Subject: [PATCH] dev-arm: Treat GICv3 reserved addresses as RES0

According to the GIC specification (IHI0069) reserved addresses in the
GIC memory map are treated as RES0.  We allow to disable this behaviour
and panic instead (reserved_res0 = False, which is what we have been
doing so far) to catch development bugs (in gem5 and in the guest SW)

Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71138
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/dev/arm/Gic.py                  |  9 +++++++++
 src/dev/arm/gic_v3.hh               | 11 +++++++++++
 src/dev/arm/gic_v3_distributor.cc   |  6 +++---
 src/dev/arm/gic_v3_redistributor.cc |  6 +++---
 4 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 41d602b86a..6fd8eb235f 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -315,6 +315,15 @@ class Gicv3(BaseGic):
 
     gicv4 = Param.Bool(False, "GIC is GICv4 compatible")
 
+    reserved_is_res0 = Param.Bool(
+        True,
+        "According to the GIC specification (IHI0069) "
+        "reserved addresses in the GIC memory map are treated as RES0. "
+        "We allow to disable this behaviour and panic instead "
+        "(reserved_res0 = False) to catch development bugs "
+        "(in gem5 and in the guest SW)",
+    )
+
     def interruptCells(self, int_type, int_num, int_trigger, partition=None):
         """
         Interupt cells generation helper:
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 2ea6a98b3b..7adb1d0f3f 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -167,6 +167,17 @@ class Gicv3 : public BaseGic, public Gicv3Registers
     Tick write(PacketPtr pkt) override;
     bool supportsVersion(GicVersion version) override;
 
+    template<typename... Args>
+    void
+    reserved(const char* fmt, Args... args) const
+    {
+        if (params().reserved_is_res0) {
+            warn(fmt, args...);
+        } else {
+            panic(fmt, args...);
+        }
+    }
+
   public:
 
     Gicv3(const Params &p);
diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 1cb485c5f5..af306929ff 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -505,8 +505,8 @@ Gicv3Distributor::read(Addr addr, size_t size, bool is_secure_access)
         return 0; // RES0
 
       default:
-        panic("Gicv3Distributor::read(): invalid offset %#x\n", addr);
-        break;
+        gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n", addr);
+        return 0; // RES0
     }
 }
 
@@ -999,7 +999,7 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size,
       }
 
       default:
-        panic("Gicv3Distributor::write(): invalid offset %#x\n", addr);
+        gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n", addr);
         break;
     }
 }
diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index e4380ef6f0..67d6e42e6b 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -377,8 +377,8 @@ Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
         return 0;
 
       default:
-        panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
-        break;
+        gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
+        return 0; // RES0
     }
 }
 
@@ -704,7 +704,7 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
       }
 
       default:
-        panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
+        gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
         break;
     }
 }