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stdlib: Update TestBoard to work with Simulator

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This change makes minor updates to the TestBoard so that it can work
nicely with the Simulator module.

This change also makes the cache hierarchy optional for the TestBoard.

Change-Id: If46d53779164e87b6fc06176355be6b4ae05aa99
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64017
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Mahyar Samani <msamani@ucdavis.edu>
This commit is contained in:
Jason Lowe-Power
2022-09-30 17:47:52 -07:00
committed by Jason Lowe-Power
parent b8e6e3aa43
commit b3372a7053
4 changed files with 36 additions and 8 deletions
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2
tests/gem5/traffic_gen/simple_traffic_run.py
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@@ -192,7 +192,7 @@ generator = generator_factory(
# tasks
motherboard = TestBoard(
clk_freq="3GHz",
processor=generator, # We pass the traffic generator as the processor.
generator=generator,
memory=memory,
cache_hierarchy=cache_hierarchy,
)