misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Restructure the existing sources in preparation of the addition of the
 * new
   Master Port.
 * Refractor names to allow for distinction of the slave and master port.
 * Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

configs/common/MemConfig.py

@@ -163,7 +163,7 @@ def config_mem(options, system):
 
     if options.tlm_memory:
         system.external_memory = m5.objects.ExternalSlave(
-            port_type="tlm",
+            port_type="tlm_slave",
             port_data=options.tlm_memory,
             port=system.membus.master,
             addr_ranges=system.mem_ranges)