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arch-arm: Add support for AArch32 PMEVCNTR*/PMEVTYPER*/PMCCFILTR (#1388)

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These registers were only handled in AArch64 mode but are also
accessible as a c14 registers for AArch32.

Change-Id: I62fe54427e96265df0589308afa1b5d665dbf210
This commit is contained in:
Alexander Richardson
2024-07-29 10:22:00 -07:00
committed by GitHub
parent b51927e7a8
commit b23a4c7806
4 changed files with 109 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/arch/arm/pmu.cc
View File

@@ -244,6 +244,9 @@ PMU::setMiscReg(int misc_reg, RegVal val)
case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
return;
case MISCREG_PMEVTYPER0...MISCREG_PMEVTYPER5:
setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0, val);
return;
case MISCREG_PMCCFILTR:
case MISCREG_PMCCFILTR_EL0:
@@ -263,6 +266,9 @@ PMU::setMiscReg(int misc_reg, RegVal val)
case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0:
setCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
return;
case MISCREG_PMEVCNTR0...MISCREG_PMEVCNTR5:
setCounterValue(misc_reg - MISCREG_PMEVCNTR0, val);
return;
case MISCREG_PMXEVCNTR_EL0:
case MISCREG_PMXEVCNTR:
@@ -354,6 +360,8 @@ PMU::readMiscRegInt(int misc_reg)
case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
return getCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0);
case MISCREG_PMEVTYPER0...MISCREG_PMEVTYPER5:
return getCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0);
case MISCREG_PMCCFILTR:
case MISCREG_PMCCFILTR_EL0:
@@ -364,11 +372,10 @@ PMU::readMiscRegInt(int misc_reg)
case MISCREG_PMXEVTYPER:
return getCounterTypeRegister(reg_pmselr.sel);
case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0: {
return getCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0) &
0xFFFFFFFF;
}
case MISCREG_PMEVCNTR0_EL0...MISCREG_PMEVCNTR5_EL0:
return getCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0) & 0xFFFFFFFF;
case MISCREG_PMEVCNTR0...MISCREG_PMEVCNTR5:
return getCounterValue(misc_reg - MISCREG_PMEVCNTR0) & 0xFFFFFFFF;
case MISCREG_PMXEVCNTR_EL0:
case MISCREG_PMXEVCNTR:

85
src/arch/arm/regs/misc.cc
View File

@@ -401,6 +401,19 @@ std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
{ MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
{ MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
{ MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
{ MiscRegNum32(15, 0, 14, 8, 0), MISCREG_PMEVCNTR0 },
{ MiscRegNum32(15, 0, 14, 8, 1), MISCREG_PMEVCNTR1 },
{ MiscRegNum32(15, 0, 14, 8, 2), MISCREG_PMEVCNTR2 },
{ MiscRegNum32(15, 0, 14, 8, 3), MISCREG_PMEVCNTR3 },
{ MiscRegNum32(15, 0, 14, 8, 4), MISCREG_PMEVCNTR4 },
{ MiscRegNum32(15, 0, 14, 8, 5), MISCREG_PMEVCNTR5 },
{ MiscRegNum32(15, 0, 14, 12, 0), MISCREG_PMEVTYPER0 },
{ MiscRegNum32(15, 0, 14, 12, 1), MISCREG_PMEVTYPER1 },
{ MiscRegNum32(15, 0, 14, 12, 2), MISCREG_PMEVTYPER2 },
{ MiscRegNum32(15, 0, 14, 12, 3), MISCREG_PMEVTYPER3 },
{ MiscRegNum32(15, 0, 14, 12, 4), MISCREG_PMEVTYPER4 },
{ MiscRegNum32(15, 0, 14, 12, 5), MISCREG_PMEVTYPER5 },
{ MiscRegNum32(15, 0, 14, 15, 7), MISCREG_PMCCFILTR },
{ MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
{ MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
{ MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
@@ -3964,6 +3977,30 @@ ISA::initializeMiscRegMetadata()
.allPrivileges();
InitReg(MISCREG_PMXEVTYPER)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR0)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR1)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR2)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR3)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR4)
.allPrivileges();
InitReg(MISCREG_PMEVCNTR5)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER0)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER1)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER2)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER3)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER4)
.allPrivileges();
InitReg(MISCREG_PMEVTYPER5)
.allPrivileges();
InitReg(MISCREG_PMCCFILTR)
.allPrivileges();
InitReg(MISCREG_PMXEVCNTR)
@@ -6142,41 +6179,41 @@ ISA::initializeMiscRegMetadata()
.mapsTo(MISCREG_CNTVOFF);
// END Generic Timer (AArch64)
InitReg(MISCREG_PMEVCNTR0_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR0);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR0);
InitReg(MISCREG_PMEVCNTR1_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR1);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR1);
InitReg(MISCREG_PMEVCNTR2_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR2);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR2);
InitReg(MISCREG_PMEVCNTR3_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR3);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR3);
InitReg(MISCREG_PMEVCNTR4_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR4);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR4);
InitReg(MISCREG_PMEVCNTR5_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVCNTR5);
.allPrivileges()
.mapsTo(MISCREG_PMEVCNTR5);
InitReg(MISCREG_PMEVTYPER0_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER0);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER0);
InitReg(MISCREG_PMEVTYPER1_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER1);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER1);
InitReg(MISCREG_PMEVTYPER2_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER2);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER2);
InitReg(MISCREG_PMEVTYPER3_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER3);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER3);
InitReg(MISCREG_PMEVTYPER4_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER4);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER4);
InitReg(MISCREG_PMEVTYPER5_EL0)
.allPrivileges();
// .mapsTo(MISCREG_PMEVTYPER5);
.allPrivileges()
.mapsTo(MISCREG_PMEVTYPER5);
InitReg(MISCREG_IL1DATA0_EL1)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_IL1DATA1_EL1)

24
src/arch/arm/regs/misc.hh
View File

@@ -376,6 +376,18 @@ namespace ArmISA
MISCREG_PMCEID1,
MISCREG_PMCCNTR,
MISCREG_PMXEVTYPER,
MISCREG_PMEVCNTR0,
MISCREG_PMEVCNTR1,
MISCREG_PMEVCNTR2,
MISCREG_PMEVCNTR3,
MISCREG_PMEVCNTR4,
MISCREG_PMEVCNTR5,
MISCREG_PMEVTYPER0,
MISCREG_PMEVTYPER1,
MISCREG_PMEVTYPER2,
MISCREG_PMEVTYPER3,
MISCREG_PMEVTYPER4,
MISCREG_PMEVTYPER5,
MISCREG_PMCCFILTR,
MISCREG_PMXEVCNTR,
MISCREG_PMUSERENR,
@@ -2125,6 +2137,18 @@ namespace ArmISA
"pmceid1",
"pmccntr",
"pmxevtyper",
"pmevcntr0",
"pmevcntr1",
"pmevcntr2",
"pmevcntr3",
"pmevcntr4",
"pmevcntr5",
"pmevtyper0",
"pmevtyper1",
"pmevtyper2",
"pmevtyper3",
"pmevtyper4",
"pmevtyper5",
"pmccfiltr",
"pmxevcntr",
"pmuserenr",

12
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -335,6 +335,18 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
{ "pmceid1", MISCREG_PMCEID1 },
{ "pmccntr", MISCREG_PMCCNTR },
{ "pmxevtyper", MISCREG_PMXEVTYPER },
{ "pmevcntr0", MISCREG_PMEVCNTR0 },
{ "pmevcntr1", MISCREG_PMEVCNTR1 },
{ "pmevcntr2", MISCREG_PMEVCNTR2 },
{ "pmevcntr3", MISCREG_PMEVCNTR3 },
{ "pmevcntr4", MISCREG_PMEVCNTR4 },
{ "pmevcntr5", MISCREG_PMEVCNTR5 },
{ "pmevtyper0", MISCREG_PMEVTYPER0 },
{ "pmevtyper1", MISCREG_PMEVTYPER1 },
{ "pmevtyper2", MISCREG_PMEVTYPER2 },
{ "pmevtyper3", MISCREG_PMEVTYPER3 },
{ "pmevtyper4", MISCREG_PMEVTYPER4 },
{ "pmevtyper5", MISCREG_PMEVTYPER5 },
{ "pmccfiltr", MISCREG_PMCCFILTR },
{ "pmxevcntr", MISCREG_PMXEVCNTR },
{ "pmuserenr", MISCREG_PMUSERENR },